atomic.cc (2657:b119b774656b) atomic.cc (2662:f24ae2d09e27)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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245 traceData->setAddr(addr);
246 }
247
248 // translate to physical address
249 Fault fault = cpuXC->translateDataReadReq(data_read_req);
250
251 // Now do the access.
252 if (fault == NoFault) {
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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245 traceData->setAddr(addr);
246 }
247
248 // translate to physical address
249 Fault fault = cpuXC->translateDataReadReq(data_read_req);
250
251 // Now do the access.
252 if (fault == NoFault) {
253 data_read_pkt->reset();
254 data_read_pkt->reinitFromRequest();
255
253 data_read_pkt->reinitFromRequest();
254
256 dcache_complete = dcachePort.sendAtomic(data_read_pkt);
255 dcache_latency = dcachePort.sendAtomic(data_read_pkt);
257 dcache_access = true;
258
259 assert(data_read_pkt->result == Packet::Success);
260 data = data_read_pkt->get<T>();
261
262 }
263
264 // This will need a new way to tell if it has a dcache attached.

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324 traceData->setAddr(addr);
325 }
326
327 // translate to physical address
328 Fault fault = cpuXC->translateDataWriteReq(data_write_req);
329
330 // Now do the access.
331 if (fault == NoFault) {
256 dcache_access = true;
257
258 assert(data_read_pkt->result == Packet::Success);
259 data = data_read_pkt->get<T>();
260
261 }
262
263 // This will need a new way to tell if it has a dcache attached.

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323 traceData->setAddr(addr);
324 }
325
326 // translate to physical address
327 Fault fault = cpuXC->translateDataWriteReq(data_write_req);
328
329 // Now do the access.
330 if (fault == NoFault) {
332 data_write_pkt->reset();
333 data = htog(data);
331 data = htog(data);
334 data_write_pkt->dataStatic(&data);
335 data_write_pkt->reinitFromRequest();
332 data_write_pkt->reinitFromRequest();
333 data_write_pkt->dataStatic(&data);
336
334
337 dcache_complete = dcachePort.sendAtomic(data_write_pkt);
335 dcache_latency = dcachePort.sendAtomic(data_write_pkt);
338 dcache_access = true;
339
340 assert(data_write_pkt->result == Packet::Success);
341
342 if (res && data_write_req->getFlags() & LOCKED) {
343 *res = data_write_req->getScResult();
344 }
345 }

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406 Tick latency = cycles(1); // instruction takes one cycle by default
407
408 for (int i = 0; i < width; ++i) {
409 numCycles++;
410
411 checkForInterrupts();
412
413 ifetch_req->resetMin();
336 dcache_access = true;
337
338 assert(data_write_pkt->result == Packet::Success);
339
340 if (res && data_write_req->getFlags() & LOCKED) {
341 *res = data_write_req->getScResult();
342 }
343 }

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404 Tick latency = cycles(1); // instruction takes one cycle by default
405
406 for (int i = 0; i < width; ++i) {
407 numCycles++;
408
409 checkForInterrupts();
410
411 ifetch_req->resetMin();
414 ifetch_pkt->reset();
415 Fault fault = setupFetchPacket(ifetch_pkt);
412 Fault fault = setupFetchRequest(ifetch_req);
416
417 if (fault == NoFault) {
413
414 if (fault == NoFault) {
418 Tick icache_complete = icachePort.sendAtomic(ifetch_pkt);
415 ifetch_pkt->reinitFromRequest();
416
417 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
419 // ifetch_req is initialized to read the instruction directly
420 // into the CPU object's inst field.
421
422 dcache_access = false; // assume no dcache access
423 preExecute();
424 fault = curStaticInst->execute(this, traceData);
425 postExecute();
426
427 if (simulate_stalls) {
428 // This calculation assumes that the icache and dcache
429 // access latencies are always a multiple of the CPU's
430 // cycle time. If not, the next tick event may get
431 // scheduled at a non-integer multiple of the CPU
432 // cycle time.
418 // ifetch_req is initialized to read the instruction directly
419 // into the CPU object's inst field.
420
421 dcache_access = false; // assume no dcache access
422 preExecute();
423 fault = curStaticInst->execute(this, traceData);
424 postExecute();
425
426 if (simulate_stalls) {
427 // This calculation assumes that the icache and dcache
428 // access latencies are always a multiple of the CPU's
429 // cycle time. If not, the next tick event may get
430 // scheduled at a non-integer multiple of the CPU
431 // cycle time.
433 Tick icache_stall = icache_complete - curTick - cycles(1);
432 Tick icache_stall = icache_latency - cycles(1);
434 Tick dcache_stall =
433 Tick dcache_stall =
435 dcache_access ? dcache_complete - curTick - cycles(1) : 0;
434 dcache_access ? dcache_latency - cycles(1) : 0;
436 latency += icache_stall + dcache_stall;
437 }
438
439 }
440
441 advancePC(fault);
442 }
443

--- 102 unchanged lines hidden --- 		435 latency += icache_stall + dcache_stall;
436 }
437
438 }
439
440 advancePC(fault);
441 }
442

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