atomic.cc (2640:266b80dd5eca) atomic.cc (2641:6d9d837e2032)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 112 unchanged lines hidden (view full) ---

121{
122 _status = Idle;
123
124 ifetch_req = new Request(true);
125 ifetch_req->setAsid(0);
126 // @todo fix me and get the real cpu iD!!!
127 ifetch_req->setCpuNum(0);
128 ifetch_req->setSize(sizeof(MachInst));
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 112 unchanged lines hidden (view full) ---

121{
122 _status = Idle;
123
124 ifetch_req = new Request(true);
125 ifetch_req->setAsid(0);
126 // @todo fix me and get the real cpu iD!!!
127 ifetch_req->setCpuNum(0);
128 ifetch_req->setSize(sizeof(MachInst));
129 ifetch_pkt = new Packet;
130 ifetch_pkt->cmd = Read;
129 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
131 ifetch_pkt->dataStatic(&inst);
130 ifetch_pkt->dataStatic(&inst);
132 ifetch_pkt->req = ifetch_req;
133 ifetch_pkt->size = sizeof(MachInst);
134 ifetch_pkt->dest = Packet::Broadcast;
135
136 data_read_req = new Request(true);
137 // @todo fix me and get the real cpu iD!!!
138 data_read_req->setCpuNum(0);
139 data_read_req->setAsid(0);
131
132 data_read_req = new Request(true);
133 // @todo fix me and get the real cpu iD!!!
134 data_read_req->setCpuNum(0);
135 data_read_req->setAsid(0);
140 data_read_pkt = new Packet;
141 data_read_pkt->cmd = Read;
136 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
137 Packet::Broadcast);
142 data_read_pkt->dataStatic(&dataReg);
138 data_read_pkt->dataStatic(&dataReg);
143 data_read_pkt->req = data_read_req;
144 data_read_pkt->dest = Packet::Broadcast;
145
146 data_write_req = new Request(true);
147 // @todo fix me and get the real cpu iD!!!
148 data_write_req->setCpuNum(0);
149 data_write_req->setAsid(0);
139
140 data_write_req = new Request(true);
141 // @todo fix me and get the real cpu iD!!!
142 data_write_req->setCpuNum(0);
143 data_write_req->setAsid(0);
150 data_write_pkt = new Packet;
151 data_write_pkt->cmd = Write;
152 data_write_pkt->req = data_write_req;
153 data_write_pkt->dest = Packet::Broadcast;
144 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
145 Packet::Broadcast);
154}
155
156
157AtomicSimpleCPU::~AtomicSimpleCPU()
158{
159}
160
161void

--- 93 unchanged lines hidden (view full) ---

255 }
256
257 // translate to physical address
258 Fault fault = cpuXC->translateDataReadReq(data_read_req);
259
260 // Now do the access.
261 if (fault == NoFault) {
262 data_read_pkt->reset();
146}
147
148
149AtomicSimpleCPU::~AtomicSimpleCPU()
150{
151}
152
153void

--- 93 unchanged lines hidden (view full) ---

247 }
248
249 // translate to physical address
250 Fault fault = cpuXC->translateDataReadReq(data_read_req);
251
252 // Now do the access.
253 if (fault == NoFault) {
254 data_read_pkt->reset();
263 data_read_pkt->addr = data_read_req->getPaddr();
264 data_read_pkt->size = sizeof(T);
255 data_read_pkt->reinitFromRequest();
265
266 dcache_complete = dcachePort.sendAtomic(data_read_pkt);
267 dcache_access = true;
268
256
257 dcache_complete = dcachePort.sendAtomic(data_read_pkt);
258 dcache_access = true;
259
269 assert(data_read_pkt->result == Success);
260 assert(data_read_pkt->result == Packet::Success);
270 data = data_read_pkt->get<T>();
271
272 }
273
274 // This will need a new way to tell if it has a dcache attached.
275 if (data_read_req->getFlags() & UNCACHEABLE)
276 recordEvent("Uncached Read");
277

--- 59 unchanged lines hidden (view full) ---

337 // translate to physical address
338 Fault fault = cpuXC->translateDataWriteReq(data_write_req);
339
340 // Now do the access.
341 if (fault == NoFault) {
342 data_write_pkt->reset();
343 data = htog(data);
344 data_write_pkt->dataStatic(&data);
261 data = data_read_pkt->get<T>();
262
263 }
264
265 // This will need a new way to tell if it has a dcache attached.
266 if (data_read_req->getFlags() & UNCACHEABLE)
267 recordEvent("Uncached Read");
268

--- 59 unchanged lines hidden (view full) ---

328 // translate to physical address
329 Fault fault = cpuXC->translateDataWriteReq(data_write_req);
330
331 // Now do the access.
332 if (fault == NoFault) {
333 data_write_pkt->reset();
334 data = htog(data);
335 data_write_pkt->dataStatic(&data);
345 data_write_pkt->addr = data_write_req->getPaddr();
346 data_write_pkt->size = sizeof(T);
336 data_write_pkt->reinitFromRequest();
347
348 dcache_complete = dcachePort.sendAtomic(data_write_pkt);
349 dcache_access = true;
350
337
338 dcache_complete = dcachePort.sendAtomic(data_write_pkt);
339 dcache_access = true;
340
351 assert(data_write_pkt->result == Success);
341 assert(data_write_pkt->result == Packet::Success);
352
353 if (res && data_write_req->getFlags() & LOCKED) {
354 *res = data_write_req->getScResult();
355 }
356 }
357
358 // This will need a new way to tell if it's hooked up to a cache or not.
359 if (data_write_req->getFlags() & UNCACHEABLE)

--- 201 unchanged lines hidden --- 		342
343 if (res && data_write_req->getFlags() & LOCKED) {
344 *res = data_write_req->getScResult();
345 }
346 }
347
348 // This will need a new way to tell if it's hooked up to a cache or not.
349 if (data_write_req->getFlags() & UNCACHEABLE)

--- 201 unchanged lines hidden ---