| atomic.cc (14219:64ff727176ba) | atomic.cc (14297:b4519e586f5e) |
|---|---|
| 1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2012-2013,2015,2017-2019 ARM Limited 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 552 unchanged lines hidden (view full) --- 561 data += frag_size; 562 563 curr_frag_id++; 564 } 565} 566 567Fault 568AtomicSimpleCPU::amoMem(Addr addr, uint8_t* data, unsigned size, | 1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2012-2013,2015,2017-2019 ARM Limited 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 552 unchanged lines hidden (view full) --- 561 data += frag_size; 562 563 curr_frag_id++; 564 } 565} 566 567Fault 568AtomicSimpleCPU::amoMem(Addr addr, uint8_t* data, unsigned size, |
| 569 Request::Flags flags, AtomicOpFunctor *amo_op) | 569 Request::Flags flags, AtomicOpFunctorPtr amo_op) |
| 570{ 571 SimpleExecContext& t_info = *threadInfo[curThread]; 572 SimpleThread* thread = t_info.thread; 573 574 // use the CPU's statically allocated amo request and packet objects 575 const RequestPtr &req = data_amo_req; 576 577 if (traceData) --- 13 unchanged lines hidden (view full) --- 591 if (secondAddr > addr) { 592 panic("AMO request should not access across a cache line boundary\n"); 593 } 594 595 dcache_latency = 0; 596 597 req->taskId(taskId()); 598 req->setVirt(0, addr, size, flags, dataMasterId(), | 570{ 571 SimpleExecContext& t_info = *threadInfo[curThread]; 572 SimpleThread* thread = t_info.thread; 573 574 // use the CPU's statically allocated amo request and packet objects 575 const RequestPtr &req = data_amo_req; 576 577 if (traceData) --- 13 unchanged lines hidden (view full) --- 591 if (secondAddr > addr) { 592 panic("AMO request should not access across a cache line boundary\n"); 593 } 594 595 dcache_latency = 0; 596 597 req->taskId(taskId()); 598 req->setVirt(0, addr, size, flags, dataMasterId(), |
| 599 thread->pcState().instAddr(), amo_op); | 599 thread->pcState().instAddr(), std::move(amo_op)); |
| 600 601 // translate to physical address 602 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 603 BaseTLB::Write); 604 605 // Now do the access. 606 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 607 // We treat AMO accesses as Write accesses with SwapReq command --- 187 unchanged lines hidden --- | 600 601 // translate to physical address 602 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 603 BaseTLB::Write); 604 605 // Now do the access. 606 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 607 // We treat AMO accesses as Write accesses with SwapReq command --- 187 unchanged lines hidden --- |