atomic.cc (12749:223c83ed9979) atomic.cc (13012:5fbc6b9c64bc)
1/*
2 * Copyright 2014 Google, Inc.
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013,2015,2017 ARM Limited
3 * Copyright (c) 2012-2013,2015,2017-2018 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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78 : BaseSimpleCPU(p),
79 tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
80 false, Event::CPU_Tick_Pri),
81 width(p->width), locked(false),
82 simulate_data_stalls(p->simulate_data_stalls),
83 simulate_inst_stalls(p->simulate_inst_stalls),
84 icachePort(name() + ".icache_port", this),
85 dcachePort(name() + ".dcache_port", this),
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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78 : BaseSimpleCPU(p),
79 tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
80 false, Event::CPU_Tick_Pri),
81 width(p->width), locked(false),
82 simulate_data_stalls(p->simulate_data_stalls),
83 simulate_inst_stalls(p->simulate_inst_stalls),
84 icachePort(name() + ".icache_port", this),
85 dcachePort(name() + ".dcache_port", this),
86 fastmem(p->fastmem), dcache_access(false), dcache_latency(0),
86 dcache_access(false), dcache_latency(0),
87 ppCommit(nullptr)
88{
89 _status = Idle;
90 ifetch_req = std::make_shared<Request>();
91 data_read_req = std::make_shared<Request>();
92 data_write_req = std::make_shared<Request>();
93}
94

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266 if (tickEvent.scheduled()) {
267 deschedule(tickEvent);
268 }
269 }
270
271 BaseCPU::suspendContext(thread_num);
272}
273
87 ppCommit(nullptr)
88{
89 _status = Idle;
90 ifetch_req = std::make_shared<Request>();
91 data_read_req = std::make_shared<Request>();
92 data_write_req = std::make_shared<Request>();
93}
94

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266 if (tickEvent.scheduled()) {
267 deschedule(tickEvent);
268 }
269 }
270
271 BaseCPU::suspendContext(thread_num);
272}
273
274Tick
275AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
276{
277 return port.sendAtomic(pkt);
278}
274
275Tick
276AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
277{
278 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
279 pkt->cmdString());
280
281 // X86 ISA: Snooping an invalidation for monitor/mwait

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359 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(),
360 BaseTLB::Read);
361
362 // Now do the access.
363 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
364 Packet pkt(req, Packet::makeReadCmd(req));
365 pkt.dataStatic(data);
366
279
280Tick
281AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
282{
283 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
284 pkt->cmdString());
285
286 // X86 ISA: Snooping an invalidation for monitor/mwait

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364 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(),
365 BaseTLB::Read);
366
367 // Now do the access.
368 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
369 Packet pkt(req, Packet::makeReadCmd(req));
370 pkt.dataStatic(data);
371
367 if (req->isMmappedIpr())
372 if (req->isMmappedIpr()) {
368 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
373 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
369 else {
370 if (fastmem && system->isMemAddr(pkt.getAddr()))
371 system->getPhysMem().access(&pkt);
372 else
373 dcache_latency += dcachePort.sendAtomic(&pkt);
374 } else {
375 dcache_latency += sendPacket(dcachePort, &pkt);
374 }
375 dcache_access = true;
376
377 assert(!pkt.isError());
378
379 if (req->isLLSC()) {
380 TheISA::handleLockedRead(thread, req);
381 }

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478 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
479 Packet pkt(req, Packet::makeWriteCmd(req));
480 pkt.dataStatic(data);
481
482 if (req->isMmappedIpr()) {
483 dcache_latency +=
484 TheISA::handleIprWrite(thread->getTC(), &pkt);
485 } else {
376 }
377 dcache_access = true;
378
379 assert(!pkt.isError());
380
381 if (req->isLLSC()) {
382 TheISA::handleLockedRead(thread, req);
383 }

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480 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
481 Packet pkt(req, Packet::makeWriteCmd(req));
482 pkt.dataStatic(data);
483
484 if (req->isMmappedIpr()) {
485 dcache_latency +=
486 TheISA::handleIprWrite(thread->getTC(), &pkt);
487 } else {
486 if (fastmem && system->isMemAddr(pkt.getAddr()))
487 system->getPhysMem().access(&pkt);
488 else
489 dcache_latency += dcachePort.sendAtomic(&pkt);
488 dcache_latency += sendPacket(dcachePort, &pkt);
490
491 // Notify other threads on this CPU of write
492 threadSnoop(&pkt, curThread);
493 }
494 dcache_access = true;
495 assert(!pkt.isError());
496
497 if (req->isSwap()) {

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598 // this code should be uncommented.
599 //Fetch more instruction memory if necessary
600 //if (decoder.needMoreBytes())
601 //{
602 icache_access = true;
603 Packet ifetch_pkt = Packet(ifetch_req, MemCmd::ReadReq);
604 ifetch_pkt.dataStatic(&inst);
605
489
490 // Notify other threads on this CPU of write
491 threadSnoop(&pkt, curThread);
492 }
493 dcache_access = true;
494 assert(!pkt.isError());
495
496 if (req->isSwap()) {

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597 // this code should be uncommented.
598 //Fetch more instruction memory if necessary
599 //if (decoder.needMoreBytes())
600 //{
601 icache_access = true;
602 Packet ifetch_pkt = Packet(ifetch_req, MemCmd::ReadReq);
603 ifetch_pkt.dataStatic(&inst);
604
606 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
607 system->getPhysMem().access(&ifetch_pkt);
608 else
609 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
605 icache_latency = sendPacket(icachePort, &ifetch_pkt);
610
611 assert(!ifetch_pkt.isError());
612
613 // ifetch_req is initialized to read the instruction directly
614 // into the CPU object's inst field.
615 //}
616 }
617

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607 assert(!ifetch_pkt.isError());
608
609 // ifetch_req is initialized to read the instruction directly
610 // into the CPU object's inst field.
611 //}
612 }
613

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