atomic.cc (12748:ae5ce8e42de7) atomic.cc (12749:223c83ed9979)
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013,2015,2017 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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64using namespace TheISA;
65
66void
67AtomicSimpleCPU::init()
68{
69 BaseSimpleCPU::init();
70
71 int cid = threadContexts[0]->contextId();
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013,2015,2017 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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64using namespace TheISA;
65
66void
67AtomicSimpleCPU::init()
68{
69 BaseSimpleCPU::init();
70
71 int cid = threadContexts[0]->contextId();
72 ifetch_req.setContext(cid);
73 data_read_req.setContext(cid);
74 data_write_req.setContext(cid);
72 ifetch_req->setContext(cid);
73 data_read_req->setContext(cid);
74 data_write_req->setContext(cid);
75}
76
77AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
78 : BaseSimpleCPU(p),
79 tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
80 false, Event::CPU_Tick_Pri),
81 width(p->width), locked(false),
82 simulate_data_stalls(p->simulate_data_stalls),
83 simulate_inst_stalls(p->simulate_inst_stalls),
84 icachePort(name() + ".icache_port", this),
85 dcachePort(name() + ".dcache_port", this),
86 fastmem(p->fastmem), dcache_access(false), dcache_latency(0),
87 ppCommit(nullptr)
88{
89 _status = Idle;
75}
76
77AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
78 : BaseSimpleCPU(p),
79 tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
80 false, Event::CPU_Tick_Pri),
81 width(p->width), locked(false),
82 simulate_data_stalls(p->simulate_data_stalls),
83 simulate_inst_stalls(p->simulate_inst_stalls),
84 icachePort(name() + ".icache_port", this),
85 dcachePort(name() + ".dcache_port", this),
86 fastmem(p->fastmem), dcache_access(false), dcache_latency(0),
87 ppCommit(nullptr)
88{
89 _status = Idle;
90 ifetch_req = std::make_shared<Request>();
91 data_read_req = std::make_shared<Request>();
92 data_write_req = std::make_shared<Request>();
90}
91
92
93AtomicSimpleCPU::~AtomicSimpleCPU()
94{
95 if (tickEvent.scheduled()) {
96 deschedule(tickEvent);
97 }

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326Fault
327AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
328 Request::Flags flags)
329{
330 SimpleExecContext& t_info = *threadInfo[curThread];
331 SimpleThread* thread = t_info.thread;
332
333 // use the CPU's statically allocated read request and packet objects
93}
94
95
96AtomicSimpleCPU::~AtomicSimpleCPU()
97{
98 if (tickEvent.scheduled()) {
99 deschedule(tickEvent);
100 }

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329Fault
330AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, unsigned size,
331 Request::Flags flags)
332{
333 SimpleExecContext& t_info = *threadInfo[curThread];
334 SimpleThread* thread = t_info.thread;
335
336 // use the CPU's statically allocated read request and packet objects
334 RequestPtr req = &data_read_req;
337 const RequestPtr &req = data_read_req;
335
336 if (traceData)
337 traceData->setMem(addr, size, flags);
338
339 //The size of the data we're trying to read.
340 int fullSize = size;
341
342 //The address of the second part of this access if it needs to be split

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430 if (data == NULL) {
431 assert(size <= 64);
432 assert(flags & Request::STORE_NO_DATA);
433 // This must be a cache block cleaning request
434 data = zero_array;
435 }
436
437 // use the CPU's statically allocated write request and packet objects
338
339 if (traceData)
340 traceData->setMem(addr, size, flags);
341
342 //The size of the data we're trying to read.
343 int fullSize = size;
344
345 //The address of the second part of this access if it needs to be split

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433 if (data == NULL) {
434 assert(size <= 64);
435 assert(flags & Request::STORE_NO_DATA);
436 // This must be a cache block cleaning request
437 data = zero_array;
438 }
439
440 // use the CPU's statically allocated write request and packet objects
438 RequestPtr req = &data_write_req;
441 const RequestPtr &req = data_write_req;
439
440 if (traceData)
441 traceData->setMem(addr, size, flags);
442
443 //The size of the data we're trying to read.
444 int fullSize = size;
445
446 //The address of the second part of this access if it needs to be split

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540
541 // Change thread if multi-threaded
542 swapActiveThread();
543
544 // Set memroy request ids to current thread
545 if (numThreads > 1) {
546 ContextID cid = threadContexts[curThread]->contextId();
547
442
443 if (traceData)
444 traceData->setMem(addr, size, flags);
445
446 //The size of the data we're trying to read.
447 int fullSize = size;
448
449 //The address of the second part of this access if it needs to be split

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543
544 // Change thread if multi-threaded
545 swapActiveThread();
546
547 // Set memroy request ids to current thread
548 if (numThreads > 1) {
549 ContextID cid = threadContexts[curThread]->contextId();
550
548 ifetch_req.setContext(cid);
549 data_read_req.setContext(cid);
550 data_write_req.setContext(cid);
551 ifetch_req->setContext(cid);
552 data_read_req->setContext(cid);
553 data_write_req->setContext(cid);
551 }
552
553 SimpleExecContext& t_info = *threadInfo[curThread];
554 SimpleThread* thread = t_info.thread;
555
556 Tick latency = 0;
557
558 for (int i = 0; i < width || locked; ++i) {

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572
573 Fault fault = NoFault;
574
575 TheISA::PCState pcState = thread->pcState();
576
577 bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
578 !curMacroStaticInst;
579 if (needToFetch) {
554 }
555
556 SimpleExecContext& t_info = *threadInfo[curThread];
557 SimpleThread* thread = t_info.thread;
558
559 Tick latency = 0;
560
561 for (int i = 0; i < width || locked; ++i) {

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575
576 Fault fault = NoFault;
577
578 TheISA::PCState pcState = thread->pcState();
579
580 bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
581 !curMacroStaticInst;
582 if (needToFetch) {
580 ifetch_req.taskId(taskId());
581 setupFetchRequest(&ifetch_req);
582 fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(),
583 ifetch_req->taskId(taskId());
584 setupFetchRequest(ifetch_req);
585 fault = thread->itb->translateAtomic(ifetch_req, thread->getTC(),
583 BaseTLB::Execute);
584 }
585
586 if (fault == NoFault) {
587 Tick icache_latency = 0;
588 bool icache_access = false;
589 dcache_access = false; // assume no dcache access
590
591 if (needToFetch) {
592 // This is commented out because the decoder would act like
593 // a tiny cache otherwise. It wouldn't be flushed when needed
594 // like the I cache. It should be flushed, and when that works
595 // this code should be uncommented.
596 //Fetch more instruction memory if necessary
597 //if (decoder.needMoreBytes())
598 //{
599 icache_access = true;
586 BaseTLB::Execute);
587 }
588
589 if (fault == NoFault) {
590 Tick icache_latency = 0;
591 bool icache_access = false;
592 dcache_access = false; // assume no dcache access
593
594 if (needToFetch) {
595 // This is commented out because the decoder would act like
596 // a tiny cache otherwise. It wouldn't be flushed when needed
597 // like the I cache. It should be flushed, and when that works
598 // this code should be uncommented.
599 //Fetch more instruction memory if necessary
600 //if (decoder.needMoreBytes())
601 //{
602 icache_access = true;
600 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq);
603 Packet ifetch_pkt = Packet(ifetch_req, MemCmd::ReadReq);
601 ifetch_pkt.dataStatic(&inst);
602
603 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
604 system->getPhysMem().access(&ifetch_pkt);
605 else
606 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
607
608 assert(!ifetch_pkt.isError());

--- 92 unchanged lines hidden --- 		604 ifetch_pkt.dataStatic(&inst);
605
606 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
607 system->getPhysMem().access(&ifetch_pkt);
608 else
609 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
610
611 assert(!ifetch_pkt.isError());

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