atomic.cc (12284:b91c036913da) atomic.cc (12355:568ec3a0c614)
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013,2015,2017 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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425 Request::Flags flags, uint64_t *res)
426{
427 SimpleExecContext& t_info = *threadInfo[curThread];
428 SimpleThread* thread = t_info.thread;
429 static uint8_t zero_array[64] = {};
430
431 if (data == NULL) {
432 assert(size <= 64);
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013,2015,2017 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 416 unchanged lines hidden (view full) ---

425 Request::Flags flags, uint64_t *res)
426{
427 SimpleExecContext& t_info = *threadInfo[curThread];
428 SimpleThread* thread = t_info.thread;
429 static uint8_t zero_array[64] = {};
430
431 if (data == NULL) {
432 assert(size <= 64);
433 assert(flags & Request::CACHE_BLOCK_ZERO);
433 assert(flags & Request::STORE_NO_DATA);
434 // This must be a cache block cleaning request
435 data = zero_array;
436 }
437
438 // use the CPU's statically allocated write request and packet objects
439 Request *req = &data_write_req;
440
441 if (traceData)

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457 while (1) {
458 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
459
460 // translate to physical address
461 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
462
463 // Now do the access.
464 if (fault == NoFault) {
434 // This must be a cache block cleaning request
435 data = zero_array;
436 }
437
438 // use the CPU's statically allocated write request and packet objects
439 Request *req = &data_write_req;
440
441 if (traceData)

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457 while (1) {
458 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
459
460 // translate to physical address
461 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
462
463 // Now do the access.
464 if (fault == NoFault) {
465 MemCmd cmd = MemCmd::WriteReq; // default
466 bool do_access = true; // flag to suppress cache access
467
468 if (req->isLLSC()) {
465 bool do_access = true; // flag to suppress cache access
466
467 if (req->isLLSC()) {
469 cmd = MemCmd::StoreCondReq;
470 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
471 } else if (req->isSwap()) {
468 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
469 } else if (req->isSwap()) {
472 cmd = MemCmd::SwapReq;
473 if (req->isCondSwap()) {
474 assert(res);
475 req->setExtraData(*res);
476 }
477 }
478
479 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
470 if (req->isCondSwap()) {
471 assert(res);
472 req->setExtraData(*res);
473 }
474 }
475
476 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
480 Packet pkt = Packet(req, cmd);
477 Packet pkt(req, Packet::makeWriteCmd(req));
481 pkt.dataStatic(data);
482
483 if (req->isMmappedIpr()) {
484 dcache_latency +=
485 TheISA::handleIprWrite(thread->getTC(), &pkt);
486 } else {
487 if (fastmem && system->isMemAddr(pkt.getAddr()))
488 system->getPhysMem().access(&pkt);

--- 215 unchanged lines hidden --- 		478 pkt.dataStatic(data);
479
480 if (req->isMmappedIpr()) {
481 dcache_latency +=
482 TheISA::handleIprWrite(thread->getTC(), &pkt);
483 } else {
484 if (fastmem && system->isMemAddr(pkt.getAddr()))
485 system->getPhysMem().access(&pkt);

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