atomic.cc (10665:aef704eaedd2) atomic.cc (10739:4cfe55719da5)
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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336 while (1) {
337 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
338
339 // translate to physical address
340 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
341
342 // Now do the access.
343 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013 ARM Limited
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 327 unchanged lines hidden (view full) ---

336 while (1) {
337 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
338
339 // translate to physical address
340 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
341
342 // Now do the access.
343 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
344 Packet pkt(req, MemCmd::ReadReq);
345 pkt.refineCommand();
344 Packet pkt(req, Packet::makeReadCmd(req));
346 pkt.dataStatic(data);
347
348 if (req->isMmappedIpr())
349 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
350 else {
351 if (fastmem && system->isMemAddr(pkt.getAddr()))
352 system->getPhysMem().access(&pkt);
353 else

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345 pkt.dataStatic(data);
346
347 if (req->isMmappedIpr())
348 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
349 else {
350 if (fastmem && system->isMemAddr(pkt.getAddr()))
351 system->getPhysMem().access(&pkt);
352 else

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