atomic.cc (10407:a9023811bf9e) atomic.cc (10464:2a0fe8bca031)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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228
229 assert(thread_num == 0);
230 assert(thread);
231
232 assert(_status == Idle);
233 assert(!tickEvent.scheduled());
234
235 notIdleFraction = 1;
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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228
229 assert(thread_num == 0);
230 assert(thread);
231
232 assert(_status == Idle);
233 assert(!tickEvent.scheduled());
234
235 notIdleFraction = 1;
236 numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
236 Cycles delta = ticksToCycles(thread->lastActivate - thread->lastSuspend);
237 numCycles += delta;
238 ppCycles->notify(delta);
237
238 //Make sure ticks are still on multiples of cycles
239 schedule(tickEvent, clockEdge(Cycles(0)));
240 _status = BaseSimpleCPU::Running;
241}
242
243
244void

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496AtomicSimpleCPU::tick()
497{
498 DPRINTF(SimpleCPU, "Tick\n");
499
500 Tick latency = 0;
501
502 for (int i = 0; i < width || locked; ++i) {
503 numCycles++;
239
240 //Make sure ticks are still on multiples of cycles
241 schedule(tickEvent, clockEdge(Cycles(0)));
242 _status = BaseSimpleCPU::Running;
243}
244
245
246void

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498AtomicSimpleCPU::tick()
499{
500 DPRINTF(SimpleCPU, "Tick\n");
501
502 Tick latency = 0;
503
504 for (int i = 0; i < width || locked; ++i) {
505 numCycles++;
506 ppCycles->notify(1);
504
505 if (!curStaticInst || !curStaticInst->isDelayedCommit())
506 checkForInterrupts();
507
508 checkPcEventQueue();
509 // We must have just got suspended by a PC event
510 if (_status == Idle) {
511 tryCompleteDrain();

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609
610 if (_status != Idle)
611 schedule(tickEvent, curTick() + latency);
612}
613
614void
615AtomicSimpleCPU::regProbePoints()
616{
507
508 if (!curStaticInst || !curStaticInst->isDelayedCommit())
509 checkForInterrupts();
510
511 checkPcEventQueue();
512 // We must have just got suspended by a PC event
513 if (_status == Idle) {
514 tryCompleteDrain();

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612
613 if (_status != Idle)
614 schedule(tickEvent, curTick() + latency);
615}
616
617void
618AtomicSimpleCPU::regProbePoints()
619{
620 BaseCPU::regProbePoints();
621
617 ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>>
618 (getProbeManager(), "Commit");
619}
620
621void
622AtomicSimpleCPU::printAddr(Addr a)
623{
624 dcachePort.printAddr(a);

--- 14 unchanged lines hidden --- 		622 ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>>
623 (getProbeManager(), "Commit");
624}
625
626void
627AtomicSimpleCPU::printAddr(Addr a)
628{
629 dcachePort.printAddr(a);

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