atomic.cc (10342:711eb0e64249) | atomic.cc (10381:ab8b8601b6ff) |
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1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 96 unchanged lines hidden (view full) --- 105 106AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 107 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 108 simulate_data_stalls(p->simulate_data_stalls), 109 simulate_inst_stalls(p->simulate_inst_stalls), 110 drain_manager(NULL), 111 icachePort(name() + ".icache_port", this), 112 dcachePort(name() + ".dcache_port", this), | 1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 96 unchanged lines hidden (view full) --- 105 106AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 107 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 108 simulate_data_stalls(p->simulate_data_stalls), 109 simulate_inst_stalls(p->simulate_inst_stalls), 110 drain_manager(NULL), 111 icachePort(name() + ".icache_port", this), 112 dcachePort(name() + ".dcache_port", this), |
113 fastmem(p->fastmem), 114 simpoint(p->simpoint_profile), 115 intervalSize(p->simpoint_interval), 116 intervalCount(0), 117 intervalDrift(0), 118 simpointStream(NULL), 119 currentBBV(0, 0), 120 currentBBVInstCount(0) | 113 fastmem(p->fastmem) |
121{ 122 _status = Idle; | 114{ 115 _status = Idle; |
123 124 if (simpoint) { 125 simpointStream = simout.create(p->simpoint_profile_file, false); 126 } | |
127} 128 129 130AtomicSimpleCPU::~AtomicSimpleCPU() 131{ 132 if (tickEvent.scheduled()) { 133 deschedule(tickEvent); 134 } | 116} 117 118 119AtomicSimpleCPU::~AtomicSimpleCPU() 120{ 121 if (tickEvent.scheduled()) { 122 deschedule(tickEvent); 123 } |
135 if (simpointStream) { 136 simout.close(simpointStream); 137 } | |
138} 139 140unsigned int 141AtomicSimpleCPU::drain(DrainManager *dm) 142{ 143 assert(!drain_manager); 144 if (switchedOut()) 145 return 0; --- 423 unchanged lines hidden (view full) --- 569 } 570 571 preExecute(); 572 573 if (curStaticInst) { 574 fault = curStaticInst->execute(this, traceData); 575 576 // keep an instruction count | 124} 125 126unsigned int 127AtomicSimpleCPU::drain(DrainManager *dm) 128{ 129 assert(!drain_manager); 130 if (switchedOut()) 131 return 0; --- 423 unchanged lines hidden (view full) --- 555 } 556 557 preExecute(); 558 559 if (curStaticInst) { 560 fault = curStaticInst->execute(this, traceData); 561 562 // keep an instruction count |
577 if (fault == NoFault) | 563 if (fault == NoFault) { |
578 countInst(); | 564 countInst(); |
565 if (!curStaticInst->isMicroop() || 566 curStaticInst->isLastMicroop()) { 567 ppCommit->notify(std::make_pair(thread, curStaticInst)); 568 } 569 } |
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579 else if (traceData && !DTRACE(ExecFaulting)) { 580 delete traceData; 581 traceData = NULL; 582 } 583 584 postExecute(); 585 } 586 587 // @todo remove me after debugging with legion done 588 if (curStaticInst && (!curStaticInst->isMicroop() || 589 curStaticInst->isFirstMicroop())) 590 instCnt++; 591 | 570 else if (traceData && !DTRACE(ExecFaulting)) { 571 delete traceData; 572 traceData = NULL; 573 } 574 575 postExecute(); 576 } 577 578 // @todo remove me after debugging with legion done 579 if (curStaticInst && (!curStaticInst->isMicroop() || 580 curStaticInst->isFirstMicroop())) 581 instCnt++; 582 |
592 // profile for SimPoints if enabled and macro inst is finished 593 if (simpoint && curStaticInst && (fault == NoFault) && 594 (!curStaticInst->isMicroop() || 595 curStaticInst->isLastMicroop())) { 596 profileSimPoint(); 597 } 598 | |
599 Tick stall_ticks = 0; 600 if (simulate_inst_stalls && icache_access) 601 stall_ticks += icache_latency; 602 603 if (simulate_data_stalls && dcache_access) 604 stall_ticks += dcache_latency; 605 606 if (stall_ticks) { --- 15 unchanged lines hidden (view full) --- 622 // instruction takes at least one cycle 623 if (latency < clockPeriod()) 624 latency = clockPeriod(); 625 626 if (_status != Idle) 627 schedule(tickEvent, curTick() + latency); 628} 629 | 583 Tick stall_ticks = 0; 584 if (simulate_inst_stalls && icache_access) 585 stall_ticks += icache_latency; 586 587 if (simulate_data_stalls && dcache_access) 588 stall_ticks += dcache_latency; 589 590 if (stall_ticks) { --- 15 unchanged lines hidden (view full) --- 606 // instruction takes at least one cycle 607 if (latency < clockPeriod()) 608 latency = clockPeriod(); 609 610 if (_status != Idle) 611 schedule(tickEvent, curTick() + latency); 612} 613 |
630 | |
631void | 614void |
632AtomicSimpleCPU::printAddr(Addr a) | 615AtomicSimpleCPU::regProbePoints() |
633{ | 616{ |
634 dcachePort.printAddr(a); | 617 ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 618 (getProbeManager(), "Commit"); |
635} 636 637void | 619} 620 621void |
638AtomicSimpleCPU::profileSimPoint() | 622AtomicSimpleCPU::printAddr(Addr a) |
639{ | 623{ |
640 if (!currentBBVInstCount) 641 currentBBV.first = thread->pcState().instAddr(); 642 643 ++intervalCount; 644 ++currentBBVInstCount; 645 646 // If inst is control inst, assume end of basic block. 647 if (curStaticInst->isControl()) { 648 currentBBV.second = thread->pcState().instAddr(); 649 650 auto map_itr = bbMap.find(currentBBV); 651 if (map_itr == bbMap.end()){ 652 // If a new (previously unseen) basic block is found, 653 // add a new unique id, record num of insts and insert into bbMap. 654 BBInfo info; 655 info.id = bbMap.size() + 1; 656 info.insts = currentBBVInstCount; 657 info.count = currentBBVInstCount; 658 bbMap.insert(std::make_pair(currentBBV, info)); 659 } else { 660 // If basic block is seen before, just increment the count by the 661 // number of insts in basic block. 662 BBInfo& info = map_itr->second; 663 info.count += currentBBVInstCount; 664 } 665 currentBBVInstCount = 0; 666 667 // Reached end of interval if the sum of the current inst count 668 // (intervalCount) and the excessive inst count from the previous 669 // interval (intervalDrift) is greater than/equal to the interval size. 670 if (intervalCount + intervalDrift >= intervalSize) { 671 // summarize interval and display BBV info 672 std::vector<pair<uint64_t, uint64_t> > counts; 673 for (auto map_itr = bbMap.begin(); map_itr != bbMap.end(); 674 ++map_itr) { 675 BBInfo& info = map_itr->second; 676 if (info.count != 0) { 677 counts.push_back(std::make_pair(info.id, info.count)); 678 info.count = 0; 679 } 680 } 681 std::sort(counts.begin(), counts.end()); 682 683 // Print output BBV info 684 *simpointStream << "T"; 685 for (auto cnt_itr = counts.begin(); cnt_itr != counts.end(); 686 ++cnt_itr) { 687 *simpointStream << ":" << cnt_itr->first 688 << ":" << cnt_itr->second << " "; 689 } 690 *simpointStream << "\n"; 691 692 intervalDrift = (intervalCount + intervalDrift) - intervalSize; 693 intervalCount = 0; 694 } 695 } | 624 dcachePort.printAddr(a); |
696} 697 698//////////////////////////////////////////////////////////////////////// 699// 700// AtomicSimpleCPU Simulation Object 701// 702AtomicSimpleCPU * 703AtomicSimpleCPUParams::create() 704{ 705 numThreads = 1; 706 if (!FullSystem && workload.size() != 1) 707 panic("only one workload allowed"); 708 return new AtomicSimpleCPU(this); 709} | 625} 626 627//////////////////////////////////////////////////////////////////////// 628// 629// AtomicSimpleCPU Simulation Object 630// 631AtomicSimpleCPU * 632AtomicSimpleCPUParams::create() 633{ 634 numThreads = 1; 635 if (!FullSystem && workload.size() != 1) 636 panic("only one workload allowed"); 637 return new AtomicSimpleCPU(this); 638} |