atomic.cc (10015:0d1467be20eb) atomic.cc (10024:fc10e1f9f124)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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296 //across a cache line boundary.
297 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
298
299 if (secondAddr > addr)
300 size = secondAddr - addr;
301
302 dcache_latency = 0;
303
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 287 unchanged lines hidden (view full) ---

296 //across a cache line boundary.
297 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
298
299 if (secondAddr > addr)
300 size = secondAddr - addr;
301
302 dcache_latency = 0;
303
304 req->taskId(taskId());
304 while (1) {
305 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
306
307 // translate to physical address
308 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
309
310 // Now do the access.
311 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {

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382 //across a cache line boundary.
383 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
384
385 if(secondAddr > addr)
386 size = secondAddr - addr;
387
388 dcache_latency = 0;
389
305 while (1) {
306 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
307
308 // translate to physical address
309 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
310
311 // Now do the access.
312 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {

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383 //across a cache line boundary.
384 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize());
385
386 if(secondAddr > addr)
387 size = secondAddr - addr;
388
389 dcache_latency = 0;
390
391 req->taskId(taskId());
390 while(1) {
391 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
392
393 // translate to physical address
394 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
395
396 // Now do the access.
397 if (fault == NoFault) {

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487
488 Fault fault = NoFault;
489
490 TheISA::PCState pcState = thread->pcState();
491
492 bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
493 !curMacroStaticInst;
494 if (needToFetch) {
392 while(1) {
393 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
394
395 // translate to physical address
396 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
397
398 // Now do the access.
399 if (fault == NoFault) {

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489
490 Fault fault = NoFault;
491
492 TheISA::PCState pcState = thread->pcState();
493
494 bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
495 !curMacroStaticInst;
496 if (needToFetch) {
497 ifetch_req.taskId(taskId());
495 setupFetchRequest(&ifetch_req);
496 fault = thread->itb->translateAtomic(&ifetch_req, tc,
497 BaseTLB::Execute);
498 }
499
500 if (fault == NoFault) {
501 Tick icache_latency = 0;
502 bool icache_access = false;

--- 165 unchanged lines hidden --- 		498 setupFetchRequest(&ifetch_req);
499 fault = thread->itb->translateAtomic(&ifetch_req, tc,
500 BaseTLB::Execute);
501 }
502
503 if (fault == NoFault) {
504 Tick icache_latency = 0;
505 bool icache_access = false;

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