1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 273 unchanged lines hidden (view full) --- 282{ 283 // use the CPU's statically allocated read request and packet objects 284 Request *req = &data_read_req; 285 286 if (traceData) { 287 traceData->setAddr(addr); 288 } 289 |
290 //The size of the data we're trying to read. 291 int fullSize = size; 292 293 //The address of the second part of this access if it needs to be split 294 //across a cache line boundary. |
295 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); |
296 297 if (secondAddr > addr) 298 size = secondAddr - addr; 299 300 dcache_latency = 0; 301 302 while (1) { 303 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); --- 64 unchanged lines hidden (view full) --- 368{ 369 // use the CPU's statically allocated write request and packet objects 370 Request *req = &data_write_req; 371 372 if (traceData) { 373 traceData->setAddr(addr); 374 } 375 |
376 //The size of the data we're trying to read. 377 int fullSize = size; 378 379 //The address of the second part of this access if it needs to be split 380 //across a cache line boundary. |
381 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); |
382 383 if(secondAddr > addr) 384 size = secondAddr - addr; 385 386 dcache_latency = 0; 387 388 while(1) { 389 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); --- 277 unchanged lines hidden --- |