1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 118 unchanged lines hidden (view full) --- 127 deschedule(tickEvent); 128 } 129} 130 131unsigned int 132AtomicSimpleCPU::drain(DrainManager *dm) 133{ 134 assert(!drain_manager); |
135 if (switchedOut()) |
136 return 0; 137 138 if (!isDrained()) { 139 DPRINTF(Drain, "Requesting drain: %s\n", pcState()); 140 drain_manager = dm; 141 return 1; 142 } else { 143 if (tickEvent.scheduled()) 144 deschedule(tickEvent); 145 146 DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 147 return 0; 148 } 149} 150 151void 152AtomicSimpleCPU::drainResume() 153{ |
154 assert(!tickEvent.scheduled()); |
155 assert(!drain_manager); |
156 if (switchedOut()) |
157 return; 158 159 DPRINTF(SimpleCPU, "Resume\n"); 160 if (system->getMemoryMode() != Enums::atomic) { 161 fatal("The atomic CPU requires the memory system to be in " 162 "'atomic' mode.\n"); 163 } 164 |
165 assert(!threadContexts.empty()); 166 if (threadContexts.size() > 1) 167 fatal("The atomic CPU only supports one thread.\n"); 168 169 if (thread->status() == ThreadContext::Active) { |
170 schedule(tickEvent, nextCycle()); |
171 _status = BaseSimpleCPU::Running; 172 } else { 173 _status = BaseSimpleCPU::Idle; 174 } |
175 176 system->totalNumInsts = 0; 177} 178 179bool 180AtomicSimpleCPU::tryCompleteDrain() 181{ 182 if (!drain_manager) --- 14 unchanged lines hidden (view full) --- 197void 198AtomicSimpleCPU::switchOut() 199{ 200 BaseSimpleCPU::switchOut(); 201 202 assert(!tickEvent.scheduled()); 203 assert(_status == BaseSimpleCPU::Running || _status == Idle); 204 assert(isDrained()); |
205} 206 207 208void 209AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 210{ 211 BaseSimpleCPU::takeOverFrom(oldCPU); 212 213 // The tick event should have been descheduled by drain() 214 assert(!tickEvent.scheduled()); 215 |
216 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 217 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 218 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too 219} 220 221 222void 223AtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) --- 365 unchanged lines hidden --- |