1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 255 unchanged lines hidden (view full) --- 264 Addr secondAddr = roundDown(addr + size - 1, blockSize); 265 266 if (secondAddr > addr) 267 size = secondAddr - addr; 268 269 dcache_latency = 0; 270 271 while (1) { |
272 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); |
273 274 // translate to physical address 275 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); 276 277 // Now do the access. 278 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 279 Packet pkt = Packet(req, 280 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq, --- 71 unchanged lines hidden (view full) --- 352 Addr secondAddr = roundDown(addr + size - 1, blockSize); 353 354 if(secondAddr > addr) 355 size = secondAddr - addr; 356 357 dcache_latency = 0; 358 359 while(1) { |
360 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); |
361 362 // translate to physical address 363 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); 364 365 // Now do the access. 366 if (fault == NoFault) { 367 MemCmd cmd = MemCmd::WriteReq; // default 368 bool do_access = true; // flag to suppress cache access --- 199 unchanged lines hidden --- |