1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 437 unchanged lines hidden (view full) --- 446Fault 447AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 448{ 449 // use the CPU's statically allocated write request and packet objects 450 Request *req = &data_write_req; 451 452 if (traceData) { 453 traceData->setAddr(addr); |
454 traceData->setData(data); |
455 } 456 457 //The block size of our peer. 458 unsigned blockSize = dcachePort.peerBlockSize(); 459 //The size of the data we're trying to read. 460 int dataSize = sizeof(T); 461 462 uint8_t * dataPtr = (uint8_t *)&data; --- 63 unchanged lines hidden (view full) --- 526 // This will need a new way to tell if it's hooked up to a cache or not. 527 if (req->isUncacheable()) 528 recordEvent("Uncached Write"); 529 530 //If there's a fault or we don't need to access a second cache line, 531 //stop now. 532 if (fault != NoFault || secondAddr <= addr) 533 { |
534 if (req->isLocked() && fault == NoFault) { 535 assert(locked); 536 locked = false; 537 } 538 if (fault != NoFault && req->isPrefetch()) { 539 return NoFault; 540 } else { 541 return fault; --- 202 unchanged lines hidden --- |