1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 65 unchanged lines hidden (view full) --- 74 else 75 panic("No Such Port\n"); 76} 77 78void 79AtomicSimpleCPU::init() 80{ 81 BaseCPU::init(); |
82#if FULL_SYSTEM 83 for (int i = 0; i < threadContexts.size(); ++i) { 84 ThreadContext *tc = threadContexts[i]; 85 86 // initialize CPU, including PC |
87 TheISA::initCPU(tc, _cpuId); |
88 } 89#endif 90 if (hasPhysMemPort) { 91 bool snoop = false; 92 AddrRangeList pmAddrList; 93 physmemPort.getPeerAddressRanges(pmAddrList, snoop); 94 physMemAddr = *pmAddrList.begin(); 95 } |
96 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 97 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 98 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too |
99} 100 101bool 102AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 103{ 104 panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 105 return true; 106} --- 124 unchanged lines hidden (view full) --- 231 schedule(tickEvent, nextCycle()); 232 break; 233 } 234 } 235 if (_status != Running) { 236 _status = Idle; 237 } 238 assert(threadContexts.size() == 1); |
239 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 240 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 241 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too |
242} 243 244 245void 246AtomicSimpleCPU::activateContext(int thread_num, int delay) 247{ 248 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 249 --- 579 unchanged lines hidden --- |