1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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778 advancePC(fault);
779 }
780
781 if (_status != Idle)
782 tickEvent.schedule(curTick + latency);
783}
784
785
786void
787AtomicSimpleCPU::printAddr(Addr a)
788{
789 dcachePort.printAddr(a);
790}
791
792
793////////////////////////////////////////////////////////////////////////
794//
795// AtomicSimpleCPU Simulation Object
796//
797AtomicSimpleCPU *
798AtomicSimpleCPUParams::create()
799{
800 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();

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