1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 65 unchanged lines hidden (view full) --- 74 else 75 panic("No Such Port\n"); 76} 77 78void 79AtomicSimpleCPU::init() 80{ 81 BaseCPU::init(); |
82 cpuId = tc->readCpuId(); |
83#if FULL_SYSTEM 84 for (int i = 0; i < threadContexts.size(); ++i) { 85 ThreadContext *tc = threadContexts[i]; 86 87 // initialize CPU, including PC |
88 TheISA::initCPU(tc, cpuId); |
89 } 90#endif 91 if (hasPhysMemPort) { 92 bool snoop = false; 93 AddrRangeList pmAddrList; 94 physmemPort.getPeerAddressRanges(pmAddrList, snoop); 95 physMemAddr = *pmAddrList.begin(); 96 } |
97 ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT 98 data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too 99 data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too |
100} 101 102bool 103AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) 104{ 105 panic("AtomicSimpleCPU doesn't expect recvTiming callback!"); 106 return true; 107} --- 50 unchanged lines hidden (view full) --- 158 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this), 159 physmemPort(name() + "-iport", this), hasPhysMemPort(false) 160{ 161 _status = Idle; 162 163 icachePort.snoopRangeSent = false; 164 dcachePort.snoopRangeSent = false; 165 |
166} 167 168 169AtomicSimpleCPU::~AtomicSimpleCPU() 170{ 171} 172 173void --- 62 unchanged lines hidden (view full) --- 236 break; 237 } 238 } 239 if (_status != Running) { 240 _status = Idle; 241 } 242 assert(threadContexts.size() == 1); 243 cpuId = tc->readCpuId(); |
244 ifetch_req.setThreadContext(cpuId, 0); // Add thread ID if we add MT 245 data_read_req.setThreadContext(cpuId, 0); // Add thread ID here too 246 data_write_req.setThreadContext(cpuId, 0); // Add thread ID here too |
247} 248 249 250void 251AtomicSimpleCPU::activateContext(int thread_num, int delay) 252{ 253 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 254 --- 573 unchanged lines hidden --- |