1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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306 dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
307 else {
308 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
309 dcache_latency = physmemPort.sendAtomic(&pkt);
310 else
311 dcache_latency = dcachePort.sendAtomic(&pkt);
312 }
313 dcache_access = true;
314
314 assert(!pkt.isError());
315
316 data = gtoh(data);
317
318 if (req->isLocked()) {
319 TheISA::handleLockedRead(thread, req);
320 }
321 }

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531 Packet::Broadcast);
532 ifetch_pkt.dataStatic(&inst);
533
534 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
535 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
536 else
537 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
538
540 assert(!ifetch_pkt.isError());
539
540 // ifetch_req is initialized to read the instruction directly
541 // into the CPU object's inst field.
542 //}
543
544 preExecute();
545
546 if(curStaticInst)

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597 params->functionTrace = function_trace;
598 params->functionTraceStart = function_trace_start;
599 params->width = width;
600 params->simulate_stalls = simulate_stalls;
601 params->system = system;
602 params->cpu_id = cpu_id;
603 params->tracer = tracer;
604
607#if FULL_SYSTEM
605 params->itb = itb;
606 params->dtb = dtb;
607#if FULL_SYSTEM
608 params->profile = profile;
609 params->do_quiesce = do_quiesce;
610 params->do_checkpoint_insts = do_checkpoint_insts;
611 params->do_statistics_insts = do_statistics_insts;
612#else
613 if (workload.size() != 1)
614 panic("only one workload allowed");
615 params->process = workload[0];
616#endif
617
618 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
619 return cpu;
620}