1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 14 unchanged lines hidden (view full) --- 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 |
31#include "arch/locked_mem.hh" |
32#include "arch/utility.hh" 33#include "cpu/exetrace.hh" 34#include "cpu/simple/atomic.hh" 35#include "mem/packet_impl.hh" 36#include "sim/builder.hh" 37#include "sim/system.hh" 38 39using namespace std; --- 89 unchanged lines hidden (view full) --- 129 130AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 131 : BaseSimpleCPU(p), tickEvent(this), 132 width(p->width), simulate_stalls(p->simulate_stalls), 133 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 134{ 135 _status = Idle; 136 |
137 ifetch_req = new Request(); |
138 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT |
139 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 140 ifetch_pkt->dataStatic(&inst); 141 142 data_read_req = new Request(); |
143 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too |
144 data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 145 Packet::Broadcast); 146 data_read_pkt->dataStatic(&dataReg); 147 148 data_write_req = new Request(); |
149 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too |
150 data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 151 Packet::Broadcast); 152} 153 154 155AtomicSimpleCPU::~AtomicSimpleCPU() 156{ 157} --- 112 unchanged lines hidden (view full) --- 270 if (fault == NoFault) { 271 pkt->reinitFromRequest(); 272 273 dcache_latency = dcachePort.sendAtomic(pkt); 274 dcache_access = true; 275 276 assert(pkt->result == Packet::Success); 277 data = pkt->get<T>(); |
278 279 if (req->isLocked()) { 280 TheISA::handleLockedRead(thread, req); 281 } |
282 } 283 284 // This will need a new way to tell if it has a dcache attached. 285 if (req->getFlags() & UNCACHEABLE) 286 recordEvent("Uncached Read"); 287 288 return fault; 289} --- 55 unchanged lines hidden (view full) --- 345 traceData->setAddr(addr); 346 } 347 348 // translate to physical address 349 Fault fault = thread->translateDataWriteReq(req); 350 351 // Now do the access. 352 if (fault == NoFault) { |
353 bool do_access = true; // flag to suppress cache access |
354 |
355 if (req->isLocked()) { 356 do_access = TheISA::handleLockedWrite(thread, req); 357 } |
358 |
359 if (do_access) { 360 data = htog(data); 361 pkt->reinitFromRequest(); 362 pkt->dataStatic(&data); |
363 |
364 dcache_latency = dcachePort.sendAtomic(pkt); 365 dcache_access = true; 366 367 assert(pkt->result == Packet::Success); |
368 } |
369 370 if (req->isLocked()) { 371 uint64_t scResult = req->getScResult(); 372 if (scResult != 0) { 373 // clear failure counter 374 thread->setStCondFailures(0); 375 } 376 if (res) { 377 *res = req->getScResult(); 378 } 379 } |
380 } 381 382 // This will need a new way to tell if it's hooked up to a cache or not. 383 if (req->getFlags() & UNCACHEABLE) 384 recordEvent("Uncached Write"); 385 386 // If the write needs to have a fault on the access, consider calling 387 // changeStatus() and changing it to "bad addr write" or something. --- 100 unchanged lines hidden (view full) --- 488 489 Param<Counter> max_insts_any_thread; 490 Param<Counter> max_insts_all_threads; 491 Param<Counter> max_loads_any_thread; 492 Param<Counter> max_loads_all_threads; 493 Param<Tick> progress_interval; 494 SimObjectParam<MemObject *> mem; 495 SimObjectParam<System *> system; |
496 Param<int> cpu_id; |
497 498#if FULL_SYSTEM 499 SimObjectParam<AlphaITB *> itb; 500 SimObjectParam<AlphaDTB *> dtb; |
501 Param<Tick> profile; 502#else 503 SimObjectParam<Process *> workload; 504#endif // FULL_SYSTEM 505 506 Param<int> clock; 507 508 Param<bool> defer_registration; --- 12 unchanged lines hidden (view full) --- 521 "terminate when all threads have reached this inst count"), 522 INIT_PARAM(max_loads_any_thread, 523 "terminate when any thread reaches this load count"), 524 INIT_PARAM(max_loads_all_threads, 525 "terminate when all threads have reached this load count"), 526 INIT_PARAM(progress_interval, "Progress interval"), 527 INIT_PARAM(mem, "memory"), 528 INIT_PARAM(system, "system object"), |
529 INIT_PARAM(cpu_id, "processor ID"), |
530 531#if FULL_SYSTEM 532 INIT_PARAM(itb, "Instruction TLB"), 533 INIT_PARAM(dtb, "Data TLB"), |
534 INIT_PARAM(profile, ""), 535#else 536 INIT_PARAM(workload, "processes to run"), 537#endif // FULL_SYSTEM 538 539 INIT_PARAM(clock, "clock speed"), 540 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), 541 INIT_PARAM(width, "cpu width"), --- 17 unchanged lines hidden (view full) --- 559 params->deferRegistration = defer_registration; 560 params->clock = clock; 561 params->functionTrace = function_trace; 562 params->functionTraceStart = function_trace_start; 563 params->width = width; 564 params->simulate_stalls = simulate_stalls; 565 params->mem = mem; 566 params->system = system; |
567 params->cpu_id = cpu_id; |
568 569#if FULL_SYSTEM 570 params->itb = itb; 571 params->dtb = dtb; |
572 params->profile = profile; 573#else 574 params->process = workload; 575#endif 576 577 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params); 578 return cpu; 579} 580 581REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU) 582 |