1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 106 unchanged lines hidden (view full) --- 115 116AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 117 : BaseSimpleCPU(p), tickEvent(this), 118 width(p->width), simulate_stalls(p->simulate_stalls), 119 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 120{ 121 _status = Idle; 122 |
123 // @todo fix me and get the real cpu id & thread number!!! 124 ifetch_req = new Request(); |
125 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast); 126 ifetch_pkt->dataStatic(&inst); 127 |
128 data_read_req = new Request(); |
129 data_read_pkt = new Packet(data_read_req, Packet::ReadReq, 130 Packet::Broadcast); 131 data_read_pkt->dataStatic(&dataReg); 132 |
133 data_write_req = new Request(); |
134 data_write_pkt = new Packet(data_write_req, Packet::WriteReq, 135 Packet::Broadcast); 136} 137 138 139AtomicSimpleCPU::~AtomicSimpleCPU() 140{ 141} --- 80 unchanged lines hidden (view full) --- 222 _status = Idle; 223} 224 225 226template <class T> 227Fault 228AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags) 229{ |
230 data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC()); |
231 232 if (traceData) { 233 traceData->setAddr(addr); 234 } 235 236 // translate to physical address 237 Fault fault = cpuXC->translateDataReadReq(data_read_req); 238 --- 58 unchanged lines hidden (view full) --- 297 return read(addr, (uint32_t&)data, flags); 298} 299 300 301template <class T> 302Fault 303AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 304{ |
305 data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC()); |
306 307 if (traceData) { 308 traceData->setAddr(addr); 309 } 310 311 // translate to physical address 312 Fault fault = cpuXC->translateDataWriteReq(data_write_req); 313 --- 74 unchanged lines hidden (view full) --- 388{ 389 Tick latency = cycles(1); // instruction takes one cycle by default 390 391 for (int i = 0; i < width; ++i) { 392 numCycles++; 393 394 checkForInterrupts(); 395 |
396 Fault fault = setupFetchRequest(ifetch_req); 397 398 if (fault == NoFault) { 399 ifetch_pkt->reinitFromRequest(); 400 401 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt); 402 // ifetch_req is initialized to read the instruction directly 403 // into the CPU object's inst field. --- 125 unchanged lines hidden --- |