1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 92 unchanged lines hidden (view full) --- 101AtomicSimpleCPU::CpuPort::recvStatusChange(Status status) 102{ 103 if (status == RangeChange) 104 return; 105 106 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!"); 107} 108 |
109void |
110AtomicSimpleCPU::CpuPort::recvRetry() 111{ 112 panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); |
113} 114 115 116AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 117 : BaseSimpleCPU(p), tickEvent(this), 118 width(p->width), simulate_stalls(p->simulate_stalls), 119 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) 120{ --- 425 unchanged lines hidden --- |