1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 411 unchanged lines hidden (view full) --- 420 // ifetch_req is initialized to read the instruction directly 421 // into the CPU object's inst field. 422 423 dcache_access = false; // assume no dcache access 424 preExecute(); 425 fault = curStaticInst->execute(this, traceData); 426 postExecute(); 427 |
428 if (simulate_stalls) { 429 // This calculation assumes that the icache and dcache 430 // access latencies are always a multiple of the CPU's 431 // cycle time. If not, the next tick event may get 432 // scheduled at a non-integer multiple of the CPU 433 // cycle time. 434 Tick icache_stall = icache_complete - curTick - cycles(1); 435 Tick dcache_stall = --- 111 unchanged lines hidden --- |