1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 103 unchanged lines hidden (view full) --- 112 panic("AtomicSimpleCPU doesn't expect recvRetry callback!"); 113 return NULL; 114} 115 116 117AtomicSimpleCPU::AtomicSimpleCPU(Params *p) 118 : BaseSimpleCPU(p), tickEvent(this), 119 width(p->width), simulate_stalls(p->simulate_stalls), |
120 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this) |
121{ 122 _status = Idle; 123 124 ifetch_req = new Request(true); 125 ifetch_req->setAsid(0); 126 // @todo fix me and get the real cpu iD!!! 127 ifetch_req->setCpuNum(0); 128 ifetch_req->setSize(sizeof(MachInst)); --- 432 unchanged lines hidden --- |