1/* 2 * Copyright 2014 Google, Inc. |
3 * Copyright (c) 2012-2013,2015,2017-2018 ARM Limited |
4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated --- 66 unchanged lines hidden (view full) --- 78 : BaseSimpleCPU(p), 79 tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick", 80 false, Event::CPU_Tick_Pri), 81 width(p->width), locked(false), 82 simulate_data_stalls(p->simulate_data_stalls), 83 simulate_inst_stalls(p->simulate_inst_stalls), 84 icachePort(name() + ".icache_port", this), 85 dcachePort(name() + ".dcache_port", this), |
86 dcache_access(false), dcache_latency(0), |
87 ppCommit(nullptr) 88{ 89 _status = Idle; 90 ifetch_req = std::make_shared<Request>(); 91 data_read_req = std::make_shared<Request>(); 92 data_write_req = std::make_shared<Request>(); 93} 94 --- 171 unchanged lines hidden (view full) --- 266 if (tickEvent.scheduled()) { 267 deschedule(tickEvent); 268 } 269 } 270 271 BaseCPU::suspendContext(thread_num); 272} 273 |
274Tick 275AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt) 276{ 277 return port.sendAtomic(pkt); 278} |
279 280Tick 281AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 282{ 283 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 284 pkt->cmdString()); 285 286 // X86 ISA: Snooping an invalidation for monitor/mwait --- 77 unchanged lines hidden (view full) --- 364 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 365 BaseTLB::Read); 366 367 // Now do the access. 368 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 369 Packet pkt(req, Packet::makeReadCmd(req)); 370 pkt.dataStatic(data); 371 |
372 if (req->isMmappedIpr()) { |
373 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); |
374 } else { 375 dcache_latency += sendPacket(dcachePort, &pkt); |
376 } 377 dcache_access = true; 378 379 assert(!pkt.isError()); 380 381 if (req->isLLSC()) { 382 TheISA::handleLockedRead(thread, req); 383 } --- 96 unchanged lines hidden (view full) --- 480 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 481 Packet pkt(req, Packet::makeWriteCmd(req)); 482 pkt.dataStatic(data); 483 484 if (req->isMmappedIpr()) { 485 dcache_latency += 486 TheISA::handleIprWrite(thread->getTC(), &pkt); 487 } else { |
488 dcache_latency += sendPacket(dcachePort, &pkt); |
489 490 // Notify other threads on this CPU of write 491 threadSnoop(&pkt, curThread); 492 } 493 dcache_access = true; 494 assert(!pkt.isError()); 495 496 if (req->isSwap()) { --- 100 unchanged lines hidden (view full) --- 597 // this code should be uncommented. 598 //Fetch more instruction memory if necessary 599 //if (decoder.needMoreBytes()) 600 //{ 601 icache_access = true; 602 Packet ifetch_pkt = Packet(ifetch_req, MemCmd::ReadReq); 603 ifetch_pkt.dataStatic(&inst); 604 |
605 icache_latency = sendPacket(icachePort, &ifetch_pkt); |
606 607 assert(!ifetch_pkt.isError()); 608 609 // ifetch_req is initialized to read the instruction directly 610 // into the CPU object's inst field. 611 //} 612 } 613 --- 86 unchanged lines hidden --- |