1/* |
2 * Copyright (c) 2012-2013 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 262 unchanged lines hidden (view full) --- 273 if (tickEvent.scheduled()) 274 deschedule(tickEvent); 275 276 notIdleFraction = 0; 277 _status = Idle; 278} 279 280 |
281Tick 282AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 283{ 284 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 285 pkt->cmdString()); 286 287 // if snoop invalidates, release any associated locks 288 if (pkt->isInvalidate()) { 289 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 290 pkt->getAddr()); 291 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 292 } 293 294 return 0; 295} 296 297void 298AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 299{ 300 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 301 pkt->cmdString()); 302 303 // if snoop invalidates, release any associated locks 304 if (pkt->isInvalidate()) { 305 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 306 pkt->getAddr()); 307 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask); 308 } 309} 310 |
311Fault 312AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 313 unsigned size, unsigned flags) 314{ 315 // use the CPU's statically allocated read request and packet objects 316 Request *req = &data_read_req; 317 318 if (traceData) { --- 108 unchanged lines hidden (view full) --- 427 428 // Now do the access. 429 if (fault == NoFault) { 430 MemCmd cmd = MemCmd::WriteReq; // default 431 bool do_access = true; // flag to suppress cache access 432 433 if (req->isLLSC()) { 434 cmd = MemCmd::StoreCondReq; |
435 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); |
436 } else if (req->isSwap()) { 437 cmd = MemCmd::SwapReq; 438 if (req->isCondSwap()) { 439 assert(res); 440 req->setExtraData(*res); 441 } 442 } 443 --- 257 unchanged lines hidden --- |