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< #include "params/AtomicSimpleCPU.hh"
---
> #include "sim/builder.hh"
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< ifetch_req = new Request();
< ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
< ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
< ifetch_pkt->dataStatic(&inst);
<
< data_read_req = new Request();
< data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
< data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
< Packet::Broadcast);
< data_read_pkt->dataStatic(&dataReg);
<
< data_write_req = new Request();
< data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
< data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
< Packet::Broadcast);
< data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq,
< Packet::Broadcast);
---
> ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
> data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
> data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
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< assert(system->getMemoryMode() == Enums::atomic);
---
> assert(system->getMemoryMode() == System::Atomic);
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< Request *req = data_read_req;
< PacketPtr pkt = data_read_pkt;
<
---
> Request *req = &data_read_req;
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< pkt->reinitFromRequest();
---
> Packet pkt = Packet(req, MemCmd::ReadReq, Packet::Broadcast);
> pkt.dataStatic(&data);
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< dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
---
> dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
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< dcache_latency = dcachePort.sendAtomic(pkt);
---
> dcache_latency = dcachePort.sendAtomic(&pkt);
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< #if !defined(NDEBUG)
< if (pkt->result != Packet::Success)
< panic("Unable to find responder for address pa = %#X va = %#X\n",
< pkt->req->getPaddr(), pkt->req->getVaddr());
< #endif
< data = pkt->get<T>();
---
> assert(!pkt.isError());
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< Request *req = data_write_req;
< PacketPtr pkt;
<
---
> Request *req = &data_write_req;
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< if (req->isSwap())
< pkt = data_swap_pkt;
< else
< pkt = data_write_pkt;
<
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> Packet pkt =
> Packet(req, req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq,
> Packet::Broadcast);
> pkt.dataStatic(&data);
>
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< pkt->reinitFromRequest();
< pkt->dataStatic(&data);
<
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< dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
---
> dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
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< dcache_latency = dcachePort.sendAtomic(pkt);
---
> dcache_latency = dcachePort.sendAtomic(&pkt);
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<
< #if !defined(NDEBUG)
< if (pkt->result != Packet::Success)
< panic("Unable to find responder for address pa = %#X va = %#X\n",
< pkt->req->getPaddr(), pkt->req->getVaddr());
< #endif
---
> assert(!pkt.isError());
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< *res = pkt->get<T>();
---
> *res = pkt.get<T>();
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< Fault fault = setupFetchRequest(ifetch_req);
---
> Fault fault = setupFetchRequest(&ifetch_req);
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< ifetch_pkt->reinitFromRequest();
---
> Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
> Packet::Broadcast);
> ifetch_pkt.dataStatic(&inst);
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< icache_latency = icachePort.sendAtomic(ifetch_pkt);
---
> icache_latency = icachePort.sendAtomic(&ifetch_pkt);
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< AtomicSimpleCPU *
< AtomicSimpleCPUParams::create()
---
> BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
>
> Param<Counter> max_insts_any_thread;
> Param<Counter> max_insts_all_threads;
> Param<Counter> max_loads_any_thread;
> Param<Counter> max_loads_all_threads;
> Param<Tick> progress_interval;
> SimObjectParam<System *> system;
> Param<int> cpu_id;
>
> #if FULL_SYSTEM
> SimObjectParam<TheISA::ITB *> itb;
> SimObjectParam<TheISA::DTB *> dtb;
> Param<Tick> profile;
>
> Param<bool> do_quiesce;
> Param<bool> do_checkpoint_insts;
> Param<bool> do_statistics_insts;
> #else
> SimObjectParam<Process *> workload;
> #endif // FULL_SYSTEM
>
> Param<int> clock;
> Param<int> phase;
>
> Param<bool> defer_registration;
> Param<int> width;
> Param<bool> function_trace;
> Param<Tick> function_trace_start;
> Param<bool> simulate_stalls;
>
> END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
>
> BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
>
> INIT_PARAM(max_insts_any_thread,
> "terminate when any thread reaches this inst count"),
> INIT_PARAM(max_insts_all_threads,
> "terminate when all threads have reached this inst count"),
> INIT_PARAM(max_loads_any_thread,
> "terminate when any thread reaches this load count"),
> INIT_PARAM(max_loads_all_threads,
> "terminate when all threads have reached this load count"),
> INIT_PARAM(progress_interval, "Progress interval"),
> INIT_PARAM(system, "system object"),
> INIT_PARAM(cpu_id, "processor ID"),
>
> #if FULL_SYSTEM
> INIT_PARAM(itb, "Instruction TLB"),
> INIT_PARAM(dtb, "Data TLB"),
> INIT_PARAM(profile, ""),
> INIT_PARAM(do_quiesce, ""),
> INIT_PARAM(do_checkpoint_insts, ""),
> INIT_PARAM(do_statistics_insts, ""),
> #else
> INIT_PARAM(workload, "processes to run"),
> #endif // FULL_SYSTEM
>
> INIT_PARAM(clock, "clock speed"),
> INIT_PARAM_DFLT(phase, "clock phase", 0),
> INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
> INIT_PARAM(width, "cpu width"),
> INIT_PARAM(function_trace, "Enable function trace"),
> INIT_PARAM(function_trace_start, "Cycle to start function trace"),
> INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
>
> END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
>
>
> CREATE_SIM_OBJECT(AtomicSimpleCPU)
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< params->name = name;
---
> params->name = getInstanceName();
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< params->tracer = tracer;
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< if (workload.size() != 1)
< panic("only one workload allowed");
< params->process = workload[0];
---
> params->process = workload;
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>
> REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
>