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> * Copyright (c) 2012 ARM Limited
> * All rights reserved.
> *
> * The license below extends only to copyright in the software and shall
> * not be construed as granting a license to any other intellectual
> * property including but not limited to intellectual property relating
> * to a hardware implementation of the functionality of the software
> * licensed hereunder. You may use the software subject to the license
> * terms below provided that you ensure that this notice is replicated
> * unmodified and in its entirety in all distributions of the software,
> * modified or unmodified, in source code or in binary form.
> *
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> #include "mem/physical.hh"
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< MasterPort &
< AtomicSimpleCPU::getMasterPort(const string &if_name, int idx)
< {
< if (if_name == "physmem_port") {
< hasPhysMemPort = true;
< return physmemPort;
< } else {
< return BaseCPU::getMasterPort(if_name, idx);
< }
< }
<
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< if (hasPhysMemPort) {
< AddrRangeList pmAddrList = physmemPort.getSlavePort().getAddrRanges();
---
> if (fastmem) {
> AddrRangeList pmAddrList = system->physmem->getAddrRanges();
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< physmemPort(name() + "-iport", this), hasPhysMemPort(false)
---
> fastmem(p->fastmem)
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< if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
< dcache_latency += physmemPort.sendAtomic(&pkt);
---
> if (fastmem && pkt.getAddr() == physMemAddr)
> dcache_latency += system->physmem->doAtomicAccess(&pkt);
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< if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
< dcache_latency += physmemPort.sendAtomic(&pkt);
---
> if (fastmem && pkt.getAddr() == physMemAddr)
> dcache_latency += system->physmem->doAtomicAccess(&pkt);
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< if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
< icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
---
> if (fastmem && ifetch_pkt.getAddr() == physMemAddr)
> icache_latency =
> system->physmem->doAtomicAccess(&ifetch_pkt);