721c721
< Fault fault = setupFetchRequest(&ifetch_req);
---
> Fault fault = NoFault;
722a723,726
> bool fromRom = isRomMicroPC(thread->readMicroPC());
> if (!fromRom)
> fault = setupFetchRequest(&ifetch_req);
>
728,734c732,739
< //Fetch more instruction memory if necessary
< //if(predecoder.needMoreBytes())
< //{
< icache_access = true;
< Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
< Packet::Broadcast);
< ifetch_pkt.dataStatic(&inst);
---
> if (!fromRom) {
> //Fetch more instruction memory if necessary
> //if(predecoder.needMoreBytes())
> //{
> icache_access = true;
> Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
> Packet::Broadcast);
> ifetch_pkt.dataStatic(&inst);
736,739c741,744
< if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
< icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
< else
< icache_latency = icachePort.sendAtomic(&ifetch_pkt);
---
> if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
> icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
> else
> icache_latency = icachePort.sendAtomic(&ifetch_pkt);
741c746
< assert(!ifetch_pkt.isError());
---
> assert(!ifetch_pkt.isError());
743,745c748,751
< // ifetch_req is initialized to read the instruction directly
< // into the CPU object's inst field.
< //}
---
> // ifetch_req is initialized to read the instruction directly
> // into the CPU object's inst field.
> //}
> }