368a369,423
> Fault
> AtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr,
> int size, unsigned flags)
> {
> // use the CPU's statically allocated read request and packet objects
> Request *req = &data_read_req;
>
> if (traceData) {
> traceData->setAddr(vaddr);
> }
>
> //The block size of our peer.
> int blockSize = dcachePort.peerBlockSize();
> //The size of the data we're trying to read.
> int dataSize = size;
>
> bool firstTimeThrough = true;
>
> //The address of the second part of this access if it needs to be split
> //across a cache line boundary.
> Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize);
>
> if(secondAddr > vaddr)
> dataSize = secondAddr - vaddr;
>
> while(1) {
> req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
>
> // translate to physical address
> Fault fault = thread->translateDataReadReq(req);
>
> //If there's a fault, return it
> if (fault != NoFault)
> return fault;
>
> if (firstTimeThrough) {
> paddr = req->getPaddr();
> firstTimeThrough = false;
> }
>
> //If we don't need to access a second cache line, stop now.
> if (secondAddr <= vaddr)
> return fault;
>
> /*
> * Set up for accessing the second cache line.
> */
>
> //Adjust the size to get the remaining bytes.
> dataSize = vaddr + size - secondAddr;
> //And access the right address.
> vaddr = secondAddr;
> }
> }
>
526a582,587
> Fault
> AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
> int size, unsigned flags)
> {
> // use the CPU's statically allocated write request and packet objects
> Request *req = &data_write_req;
527a589,640
> if (traceData) {
> traceData->setAddr(vaddr);
> }
>
> //The block size of our peer.
> int blockSize = dcachePort.peerBlockSize();
>
> //The address of the second part of this access if it needs to be split
> //across a cache line boundary.
> Addr secondAddr = roundDown(vaddr + size - 1, blockSize);
>
> //The size of the data we're trying to read.
> int dataSize = size;
>
> bool firstTimeThrough = true;
>
> if(secondAddr > vaddr)
> dataSize = secondAddr - vaddr;
>
> dcache_latency = 0;
>
> while(1) {
> req->setVirt(0, vaddr, flags, flags, thread->readPC());
>
> // translate to physical address
> Fault fault = thread->translateDataWriteReq(req);
>
> //If there's a fault or we don't need to access a second cache line,
> //stop now.
> if (fault != NoFault)
> return fault;
>
> if (firstTimeThrough) {
> paddr = req->getPaddr();
> firstTimeThrough = false;
> }
>
> if (secondAddr <= vaddr)
> return fault;
>
> /*
> * Set up for accessing the second cache line.
> */
>
> //Adjust the size to get the remaining bytes.
> dataSize = vaddr + size - secondAddr;
> //And access the right address.
> vaddr = secondAddr;
> }
> }
>
>