503c503,505
< ifetch_pkt->reinitFromRequest();
---
> Tick icache_latency = 0;
> bool icache_access = false;
> dcache_access = false; // assume no dcache access
505,507c507,511
< Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
< // ifetch_req is initialized to read the instruction directly
< // into the CPU object's inst field.
---
> //Fetch more instruction memory if necessary
> if(predecoder.needMoreBytes())
> {
> icache_access = true;
> ifetch_pkt->reinitFromRequest();
509c513,517
< dcache_access = false; // assume no dcache access
---
> icache_latency = icachePort.sendAtomic(ifetch_pkt);
> // ifetch_req is initialized to read the instruction directly
> // into the CPU object's inst field.
> }
>
512,513c520,524
< fault = curStaticInst->execute(this, traceData);
< postExecute();
---
> if(curStaticInst)
> {
> fault = curStaticInst->execute(this, traceData);
> postExecute();
> }
521c532,533
< Tick icache_stall = icache_latency - cycles(1);
---
> Tick icache_stall =
> icache_access ? icache_latency - cycles(1) : 0;
532,533c544,545
<
< advancePC(fault);
---
> if(predecoder.needMoreBytes())
> advancePC(fault);