31a32
> #include "arch/mmaped_ipr.hh"
79a81,83
> // initialize the mem pointers
> tc->init();
>
240,246d243
<
< #if FULL_SYSTEM
< // Connect the ThreadContext's memory ports (Functional/Virtual
< // Ports)
< tc->connectMemPorts();
< #endif
<
292c289,292
< dcache_latency = dcachePort.sendAtomic(pkt);
---
> if (req->isMmapedIpr())
> dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
> else
> dcache_latency = dcachePort.sendAtomic(pkt);
379d378
< data = htog(data);
383c382,387
< dcache_latency = dcachePort.sendAtomic(pkt);
---
> if (req->isMmapedIpr()) {
> dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
> } else {
> data = htog(data);
> dcache_latency = dcachePort.sendAtomic(pkt);
> }