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< * Copyright (c) 2012-2013,2015,2017 ARM Limited
---
> * Copyright (c) 2012-2013,2015,2017-2018 ARM Limited
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< fastmem(p->fastmem), dcache_access(false), dcache_latency(0),
---
> dcache_access(false), dcache_latency(0),
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> Tick
> AtomicSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
> {
> return port.sendAtomic(pkt);
> }
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< if (req->isMmappedIpr())
---
> if (req->isMmappedIpr()) {
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< else {
< if (fastmem && system->isMemAddr(pkt.getAddr()))
< system->getPhysMem().access(&pkt);
< else
< dcache_latency += dcachePort.sendAtomic(&pkt);
---
> } else {
> dcache_latency += sendPacket(dcachePort, &pkt);
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< if (fastmem && system->isMemAddr(pkt.getAddr()))
< system->getPhysMem().access(&pkt);
< else
< dcache_latency += dcachePort.sendAtomic(&pkt);
---
> dcache_latency += sendPacket(dcachePort, &pkt);
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< if (fastmem && system->isMemAddr(ifetch_pkt.getAddr()))
< system->getPhysMem().access(&ifetch_pkt);
< else
< icache_latency = icachePort.sendAtomic(&ifetch_pkt);
---
> icache_latency = sendPacket(icachePort, &ifetch_pkt);