1/*
| 1/*
|
| 2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
|
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmapped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "config/the_isa.hh"
36#include "cpu/simple/atomic.hh"
37#include "cpu/exetrace.hh"
38#include "debug/ExecFaulting.hh"
39#include "debug/SimpleCPU.hh"
40#include "mem/packet.hh"
41#include "mem/packet_access.hh"
| 14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/simple/atomic.hh"
49#include "cpu/exetrace.hh"
50#include "debug/ExecFaulting.hh"
51#include "debug/SimpleCPU.hh"
52#include "mem/packet.hh"
53#include "mem/packet_access.hh"
|
| 54#include "mem/physical.hh"
|
42#include "params/AtomicSimpleCPU.hh"
43#include "sim/faults.hh"
44#include "sim/system.hh"
45#include "sim/full_system.hh"
46
47using namespace std;
48using namespace TheISA;
49
50AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
51 : Event(CPU_Tick_Pri), cpu(c)
52{
53}
54
55
56void
57AtomicSimpleCPU::TickEvent::process()
58{
59 cpu->tick();
60}
61
62const char *
63AtomicSimpleCPU::TickEvent::description() const
64{
65 return "AtomicSimpleCPU tick";
66}
67
| 55#include "params/AtomicSimpleCPU.hh"
56#include "sim/faults.hh"
57#include "sim/system.hh"
58#include "sim/full_system.hh"
59
60using namespace std;
61using namespace TheISA;
62
63AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
64 : Event(CPU_Tick_Pri), cpu(c)
65{
66}
67
68
69void
70AtomicSimpleCPU::TickEvent::process()
71{
72 cpu->tick();
73}
74
75const char *
76AtomicSimpleCPU::TickEvent::description() const
77{
78 return "AtomicSimpleCPU tick";
79}
80
|
68MasterPort &
69AtomicSimpleCPU::getMasterPort(const string &if_name, int idx)
70{
71 if (if_name == "physmem_port") {
72 hasPhysMemPort = true;
73 return physmemPort;
74 } else {
75 return BaseCPU::getMasterPort(if_name, idx);
76 }
77}
78
| |
79void
80AtomicSimpleCPU::init()
81{
82 BaseCPU::init();
83
84 // Initialise the ThreadContext's memory proxies
85 tcBase()->initMemProxies(tcBase());
86
87 if (FullSystem) {
88 ThreadID size = threadContexts.size();
89 for (ThreadID i = 0; i < size; ++i) {
90 ThreadContext *tc = threadContexts[i];
91 // initialize CPU, including PC
92 TheISA::initCPU(tc, tc->contextId());
93 }
94 }
95
| 81void
82AtomicSimpleCPU::init()
83{
84 BaseCPU::init();
85
86 // Initialise the ThreadContext's memory proxies
87 tcBase()->initMemProxies(tcBase());
88
89 if (FullSystem) {
90 ThreadID size = threadContexts.size();
91 for (ThreadID i = 0; i < size; ++i) {
92 ThreadContext *tc = threadContexts[i];
93 // initialize CPU, including PC
94 TheISA::initCPU(tc, tc->contextId());
95 }
96 }
97
|
96 if (hasPhysMemPort) {
97 AddrRangeList pmAddrList = physmemPort.getSlavePort().getAddrRanges();
| 98 if (fastmem) {
99 AddrRangeList pmAddrList = system->physmem->getAddrRanges();
|
98 physMemAddr = *pmAddrList.begin();
99 }
100 // Atomic doesn't do MT right now, so contextId == threadId
101 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
102 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
103 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
104}
105
106AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
107 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
108 simulate_data_stalls(p->simulate_data_stalls),
109 simulate_inst_stalls(p->simulate_inst_stalls),
110 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
| 100 physMemAddr = *pmAddrList.begin();
101 }
102 // Atomic doesn't do MT right now, so contextId == threadId
103 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
104 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
105 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
106}
107
108AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
109 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
110 simulate_data_stalls(p->simulate_data_stalls),
111 simulate_inst_stalls(p->simulate_inst_stalls),
112 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
|
111 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
| 113 fastmem(p->fastmem)
|
112{
113 _status = Idle;
114}
115
116
117AtomicSimpleCPU::~AtomicSimpleCPU()
118{
119 if (tickEvent.scheduled()) {
120 deschedule(tickEvent);
121 }
122}
123
124void
125AtomicSimpleCPU::serialize(ostream &os)
126{
127 SimObject::State so_state = SimObject::getState();
128 SERIALIZE_ENUM(so_state);
129 SERIALIZE_SCALAR(locked);
130 BaseSimpleCPU::serialize(os);
131 nameOut(os, csprintf("%s.tickEvent", name()));
132 tickEvent.serialize(os);
133}
134
135void
136AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
137{
138 SimObject::State so_state;
139 UNSERIALIZE_ENUM(so_state);
140 UNSERIALIZE_SCALAR(locked);
141 BaseSimpleCPU::unserialize(cp, section);
142 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
143}
144
145void
146AtomicSimpleCPU::resume()
147{
148 if (_status == Idle || _status == SwitchedOut)
149 return;
150
151 DPRINTF(SimpleCPU, "Resume\n");
152 assert(system->getMemoryMode() == Enums::atomic);
153
154 changeState(SimObject::Running);
155 if (thread->status() == ThreadContext::Active) {
156 if (!tickEvent.scheduled())
157 schedule(tickEvent, nextCycle());
158 }
159 system->totalNumInsts = 0;
160}
161
162void
163AtomicSimpleCPU::switchOut()
164{
165 assert(_status == Running || _status == Idle);
166 _status = SwitchedOut;
167
168 tickEvent.squash();
169}
170
171
172void
173AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
174{
175 BaseCPU::takeOverFrom(oldCPU);
176
177 assert(!tickEvent.scheduled());
178
179 // if any of this CPU's ThreadContexts are active, mark the CPU as
180 // running and schedule its tick event.
181 ThreadID size = threadContexts.size();
182 for (ThreadID i = 0; i < size; ++i) {
183 ThreadContext *tc = threadContexts[i];
184 if (tc->status() == ThreadContext::Active && _status != Running) {
185 _status = Running;
186 schedule(tickEvent, nextCycle());
187 break;
188 }
189 }
190 if (_status != Running) {
191 _status = Idle;
192 }
193 assert(threadContexts.size() == 1);
194 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
195 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
196 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
197}
198
199
200void
201AtomicSimpleCPU::activateContext(ThreadID thread_num, int delay)
202{
203 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
204
205 assert(thread_num == 0);
206 assert(thread);
207
208 assert(_status == Idle);
209 assert(!tickEvent.scheduled());
210
211 notIdleFraction++;
212 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
213
214 //Make sure ticks are still on multiples of cycles
215 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
216 _status = Running;
217}
218
219
220void
221AtomicSimpleCPU::suspendContext(ThreadID thread_num)
222{
223 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
224
225 assert(thread_num == 0);
226 assert(thread);
227
228 if (_status == Idle)
229 return;
230
231 assert(_status == Running);
232
233 // tick event may not be scheduled if this gets called from inside
234 // an instruction's execution, e.g. "quiesce"
235 if (tickEvent.scheduled())
236 deschedule(tickEvent);
237
238 notIdleFraction--;
239 _status = Idle;
240}
241
242
243Fault
244AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
245 unsigned size, unsigned flags)
246{
247 // use the CPU's statically allocated read request and packet objects
248 Request *req = &data_read_req;
249
250 if (traceData) {
251 traceData->setAddr(addr);
252 }
253
254 //The block size of our peer.
255 unsigned blockSize = dcachePort.peerBlockSize();
256 //The size of the data we're trying to read.
257 int fullSize = size;
258
259 //The address of the second part of this access if it needs to be split
260 //across a cache line boundary.
261 Addr secondAddr = roundDown(addr + size - 1, blockSize);
262
263 if (secondAddr > addr)
264 size = secondAddr - addr;
265
266 dcache_latency = 0;
267
268 while (1) {
269 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
270
271 // translate to physical address
272 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
273
274 // Now do the access.
275 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
276 Packet pkt = Packet(req,
277 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
278 Packet::Broadcast);
279 pkt.dataStatic(data);
280
281 if (req->isMmappedIpr())
282 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
283 else {
| 114{
115 _status = Idle;
116}
117
118
119AtomicSimpleCPU::~AtomicSimpleCPU()
120{
121 if (tickEvent.scheduled()) {
122 deschedule(tickEvent);
123 }
124}
125
126void
127AtomicSimpleCPU::serialize(ostream &os)
128{
129 SimObject::State so_state = SimObject::getState();
130 SERIALIZE_ENUM(so_state);
131 SERIALIZE_SCALAR(locked);
132 BaseSimpleCPU::serialize(os);
133 nameOut(os, csprintf("%s.tickEvent", name()));
134 tickEvent.serialize(os);
135}
136
137void
138AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
139{
140 SimObject::State so_state;
141 UNSERIALIZE_ENUM(so_state);
142 UNSERIALIZE_SCALAR(locked);
143 BaseSimpleCPU::unserialize(cp, section);
144 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
145}
146
147void
148AtomicSimpleCPU::resume()
149{
150 if (_status == Idle || _status == SwitchedOut)
151 return;
152
153 DPRINTF(SimpleCPU, "Resume\n");
154 assert(system->getMemoryMode() == Enums::atomic);
155
156 changeState(SimObject::Running);
157 if (thread->status() == ThreadContext::Active) {
158 if (!tickEvent.scheduled())
159 schedule(tickEvent, nextCycle());
160 }
161 system->totalNumInsts = 0;
162}
163
164void
165AtomicSimpleCPU::switchOut()
166{
167 assert(_status == Running || _status == Idle);
168 _status = SwitchedOut;
169
170 tickEvent.squash();
171}
172
173
174void
175AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
176{
177 BaseCPU::takeOverFrom(oldCPU);
178
179 assert(!tickEvent.scheduled());
180
181 // if any of this CPU's ThreadContexts are active, mark the CPU as
182 // running and schedule its tick event.
183 ThreadID size = threadContexts.size();
184 for (ThreadID i = 0; i < size; ++i) {
185 ThreadContext *tc = threadContexts[i];
186 if (tc->status() == ThreadContext::Active && _status != Running) {
187 _status = Running;
188 schedule(tickEvent, nextCycle());
189 break;
190 }
191 }
192 if (_status != Running) {
193 _status = Idle;
194 }
195 assert(threadContexts.size() == 1);
196 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
197 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
198 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
199}
200
201
202void
203AtomicSimpleCPU::activateContext(ThreadID thread_num, int delay)
204{
205 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
206
207 assert(thread_num == 0);
208 assert(thread);
209
210 assert(_status == Idle);
211 assert(!tickEvent.scheduled());
212
213 notIdleFraction++;
214 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
215
216 //Make sure ticks are still on multiples of cycles
217 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
218 _status = Running;
219}
220
221
222void
223AtomicSimpleCPU::suspendContext(ThreadID thread_num)
224{
225 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
226
227 assert(thread_num == 0);
228 assert(thread);
229
230 if (_status == Idle)
231 return;
232
233 assert(_status == Running);
234
235 // tick event may not be scheduled if this gets called from inside
236 // an instruction's execution, e.g. "quiesce"
237 if (tickEvent.scheduled())
238 deschedule(tickEvent);
239
240 notIdleFraction--;
241 _status = Idle;
242}
243
244
245Fault
246AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
247 unsigned size, unsigned flags)
248{
249 // use the CPU's statically allocated read request and packet objects
250 Request *req = &data_read_req;
251
252 if (traceData) {
253 traceData->setAddr(addr);
254 }
255
256 //The block size of our peer.
257 unsigned blockSize = dcachePort.peerBlockSize();
258 //The size of the data we're trying to read.
259 int fullSize = size;
260
261 //The address of the second part of this access if it needs to be split
262 //across a cache line boundary.
263 Addr secondAddr = roundDown(addr + size - 1, blockSize);
264
265 if (secondAddr > addr)
266 size = secondAddr - addr;
267
268 dcache_latency = 0;
269
270 while (1) {
271 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
272
273 // translate to physical address
274 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
275
276 // Now do the access.
277 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
278 Packet pkt = Packet(req,
279 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
280 Packet::Broadcast);
281 pkt.dataStatic(data);
282
283 if (req->isMmappedIpr())
284 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
285 else {
|
284 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
285 dcache_latency += physmemPort.sendAtomic(&pkt);
| 286 if (fastmem && pkt.getAddr() == physMemAddr)
287 dcache_latency += system->physmem->doAtomicAccess(&pkt);
|
286 else
287 dcache_latency += dcachePort.sendAtomic(&pkt);
288 }
289 dcache_access = true;
290
291 assert(!pkt.isError());
292
293 if (req->isLLSC()) {
294 TheISA::handleLockedRead(thread, req);
295 }
296 }
297
298 //If there's a fault, return it
299 if (fault != NoFault) {
300 if (req->isPrefetch()) {
301 return NoFault;
302 } else {
303 return fault;
304 }
305 }
306
307 //If we don't need to access a second cache line, stop now.
308 if (secondAddr <= addr)
309 {
310 if (req->isLocked() && fault == NoFault) {
311 assert(!locked);
312 locked = true;
313 }
314 return fault;
315 }
316
317 /*
318 * Set up for accessing the second cache line.
319 */
320
321 //Move the pointer we're reading into to the correct location.
322 data += size;
323 //Adjust the size to get the remaining bytes.
324 size = addr + fullSize - secondAddr;
325 //And access the right address.
326 addr = secondAddr;
327 }
328}
329
330
331Fault
332AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
333 Addr addr, unsigned flags, uint64_t *res)
334{
335 // use the CPU's statically allocated write request and packet objects
336 Request *req = &data_write_req;
337
338 if (traceData) {
339 traceData->setAddr(addr);
340 }
341
342 //The block size of our peer.
343 unsigned blockSize = dcachePort.peerBlockSize();
344 //The size of the data we're trying to read.
345 int fullSize = size;
346
347 //The address of the second part of this access if it needs to be split
348 //across a cache line boundary.
349 Addr secondAddr = roundDown(addr + size - 1, blockSize);
350
351 if(secondAddr > addr)
352 size = secondAddr - addr;
353
354 dcache_latency = 0;
355
356 while(1) {
357 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
358
359 // translate to physical address
360 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
361
362 // Now do the access.
363 if (fault == NoFault) {
364 MemCmd cmd = MemCmd::WriteReq; // default
365 bool do_access = true; // flag to suppress cache access
366
367 if (req->isLLSC()) {
368 cmd = MemCmd::StoreCondReq;
369 do_access = TheISA::handleLockedWrite(thread, req);
370 } else if (req->isSwap()) {
371 cmd = MemCmd::SwapReq;
372 if (req->isCondSwap()) {
373 assert(res);
374 req->setExtraData(*res);
375 }
376 }
377
378 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
379 Packet pkt = Packet(req, cmd, Packet::Broadcast);
380 pkt.dataStatic(data);
381
382 if (req->isMmappedIpr()) {
383 dcache_latency +=
384 TheISA::handleIprWrite(thread->getTC(), &pkt);
385 } else {
| 288 else
289 dcache_latency += dcachePort.sendAtomic(&pkt);
290 }
291 dcache_access = true;
292
293 assert(!pkt.isError());
294
295 if (req->isLLSC()) {
296 TheISA::handleLockedRead(thread, req);
297 }
298 }
299
300 //If there's a fault, return it
301 if (fault != NoFault) {
302 if (req->isPrefetch()) {
303 return NoFault;
304 } else {
305 return fault;
306 }
307 }
308
309 //If we don't need to access a second cache line, stop now.
310 if (secondAddr <= addr)
311 {
312 if (req->isLocked() && fault == NoFault) {
313 assert(!locked);
314 locked = true;
315 }
316 return fault;
317 }
318
319 /*
320 * Set up for accessing the second cache line.
321 */
322
323 //Move the pointer we're reading into to the correct location.
324 data += size;
325 //Adjust the size to get the remaining bytes.
326 size = addr + fullSize - secondAddr;
327 //And access the right address.
328 addr = secondAddr;
329 }
330}
331
332
333Fault
334AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
335 Addr addr, unsigned flags, uint64_t *res)
336{
337 // use the CPU's statically allocated write request and packet objects
338 Request *req = &data_write_req;
339
340 if (traceData) {
341 traceData->setAddr(addr);
342 }
343
344 //The block size of our peer.
345 unsigned blockSize = dcachePort.peerBlockSize();
346 //The size of the data we're trying to read.
347 int fullSize = size;
348
349 //The address of the second part of this access if it needs to be split
350 //across a cache line boundary.
351 Addr secondAddr = roundDown(addr + size - 1, blockSize);
352
353 if(secondAddr > addr)
354 size = secondAddr - addr;
355
356 dcache_latency = 0;
357
358 while(1) {
359 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr());
360
361 // translate to physical address
362 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
363
364 // Now do the access.
365 if (fault == NoFault) {
366 MemCmd cmd = MemCmd::WriteReq; // default
367 bool do_access = true; // flag to suppress cache access
368
369 if (req->isLLSC()) {
370 cmd = MemCmd::StoreCondReq;
371 do_access = TheISA::handleLockedWrite(thread, req);
372 } else if (req->isSwap()) {
373 cmd = MemCmd::SwapReq;
374 if (req->isCondSwap()) {
375 assert(res);
376 req->setExtraData(*res);
377 }
378 }
379
380 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
381 Packet pkt = Packet(req, cmd, Packet::Broadcast);
382 pkt.dataStatic(data);
383
384 if (req->isMmappedIpr()) {
385 dcache_latency +=
386 TheISA::handleIprWrite(thread->getTC(), &pkt);
387 } else {
|
386 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
387 dcache_latency += physmemPort.sendAtomic(&pkt);
| 388 if (fastmem && pkt.getAddr() == physMemAddr)
389 dcache_latency += system->physmem->doAtomicAccess(&pkt);
|
388 else
389 dcache_latency += dcachePort.sendAtomic(&pkt);
390 }
391 dcache_access = true;
392 assert(!pkt.isError());
393
394 if (req->isSwap()) {
395 assert(res);
396 memcpy(res, pkt.getPtr<uint8_t>(), fullSize);
397 }
398 }
399
400 if (res && !req->isSwap()) {
401 *res = req->getExtraData();
402 }
403 }
404
405 //If there's a fault or we don't need to access a second cache line,
406 //stop now.
407 if (fault != NoFault || secondAddr <= addr)
408 {
409 if (req->isLocked() && fault == NoFault) {
410 assert(locked);
411 locked = false;
412 }
413 if (fault != NoFault && req->isPrefetch()) {
414 return NoFault;
415 } else {
416 return fault;
417 }
418 }
419
420 /*
421 * Set up for accessing the second cache line.
422 */
423
424 //Move the pointer we're reading into to the correct location.
425 data += size;
426 //Adjust the size to get the remaining bytes.
427 size = addr + fullSize - secondAddr;
428 //And access the right address.
429 addr = secondAddr;
430 }
431}
432
433
434void
435AtomicSimpleCPU::tick()
436{
437 DPRINTF(SimpleCPU, "Tick\n");
438
439 Tick latency = 0;
440
441 for (int i = 0; i < width || locked; ++i) {
442 numCycles++;
443
444 if (!curStaticInst || !curStaticInst->isDelayedCommit())
445 checkForInterrupts();
446
447 checkPcEventQueue();
448 // We must have just got suspended by a PC event
449 if (_status == Idle)
450 return;
451
452 Fault fault = NoFault;
453
454 TheISA::PCState pcState = thread->pcState();
455
456 bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
457 !curMacroStaticInst;
458 if (needToFetch) {
459 setupFetchRequest(&ifetch_req);
460 fault = thread->itb->translateAtomic(&ifetch_req, tc,
461 BaseTLB::Execute);
462 }
463
464 if (fault == NoFault) {
465 Tick icache_latency = 0;
466 bool icache_access = false;
467 dcache_access = false; // assume no dcache access
468
469 if (needToFetch) {
470 // This is commented out because the predecoder would act like
471 // a tiny cache otherwise. It wouldn't be flushed when needed
472 // like the I cache. It should be flushed, and when that works
473 // this code should be uncommented.
474 //Fetch more instruction memory if necessary
475 //if(predecoder.needMoreBytes())
476 //{
477 icache_access = true;
478 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
479 Packet::Broadcast);
480 ifetch_pkt.dataStatic(&inst);
481
| 390 else
391 dcache_latency += dcachePort.sendAtomic(&pkt);
392 }
393 dcache_access = true;
394 assert(!pkt.isError());
395
396 if (req->isSwap()) {
397 assert(res);
398 memcpy(res, pkt.getPtr<uint8_t>(), fullSize);
399 }
400 }
401
402 if (res && !req->isSwap()) {
403 *res = req->getExtraData();
404 }
405 }
406
407 //If there's a fault or we don't need to access a second cache line,
408 //stop now.
409 if (fault != NoFault || secondAddr <= addr)
410 {
411 if (req->isLocked() && fault == NoFault) {
412 assert(locked);
413 locked = false;
414 }
415 if (fault != NoFault && req->isPrefetch()) {
416 return NoFault;
417 } else {
418 return fault;
419 }
420 }
421
422 /*
423 * Set up for accessing the second cache line.
424 */
425
426 //Move the pointer we're reading into to the correct location.
427 data += size;
428 //Adjust the size to get the remaining bytes.
429 size = addr + fullSize - secondAddr;
430 //And access the right address.
431 addr = secondAddr;
432 }
433}
434
435
436void
437AtomicSimpleCPU::tick()
438{
439 DPRINTF(SimpleCPU, "Tick\n");
440
441 Tick latency = 0;
442
443 for (int i = 0; i < width || locked; ++i) {
444 numCycles++;
445
446 if (!curStaticInst || !curStaticInst->isDelayedCommit())
447 checkForInterrupts();
448
449 checkPcEventQueue();
450 // We must have just got suspended by a PC event
451 if (_status == Idle)
452 return;
453
454 Fault fault = NoFault;
455
456 TheISA::PCState pcState = thread->pcState();
457
458 bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
459 !curMacroStaticInst;
460 if (needToFetch) {
461 setupFetchRequest(&ifetch_req);
462 fault = thread->itb->translateAtomic(&ifetch_req, tc,
463 BaseTLB::Execute);
464 }
465
466 if (fault == NoFault) {
467 Tick icache_latency = 0;
468 bool icache_access = false;
469 dcache_access = false; // assume no dcache access
470
471 if (needToFetch) {
472 // This is commented out because the predecoder would act like
473 // a tiny cache otherwise. It wouldn't be flushed when needed
474 // like the I cache. It should be flushed, and when that works
475 // this code should be uncommented.
476 //Fetch more instruction memory if necessary
477 //if(predecoder.needMoreBytes())
478 //{
479 icache_access = true;
480 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
481 Packet::Broadcast);
482 ifetch_pkt.dataStatic(&inst);
483
|
482 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
483 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
| 484 if (fastmem && ifetch_pkt.getAddr() == physMemAddr)
485 icache_latency =
486 system->physmem->doAtomicAccess(&ifetch_pkt);
|
484 else
485 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
486
487 assert(!ifetch_pkt.isError());
488
489 // ifetch_req is initialized to read the instruction directly
490 // into the CPU object's inst field.
491 //}
492 }
493
494 preExecute();
495
496 if (curStaticInst) {
497 fault = curStaticInst->execute(this, traceData);
498
499 // keep an instruction count
500 if (fault == NoFault)
501 countInst();
502 else if (traceData && !DTRACE(ExecFaulting)) {
503 delete traceData;
504 traceData = NULL;
505 }
506
507 postExecute();
508 }
509
510 // @todo remove me after debugging with legion done
511 if (curStaticInst && (!curStaticInst->isMicroop() ||
512 curStaticInst->isFirstMicroop()))
513 instCnt++;
514
515 Tick stall_ticks = 0;
516 if (simulate_inst_stalls && icache_access)
517 stall_ticks += icache_latency;
518
519 if (simulate_data_stalls && dcache_access)
520 stall_ticks += dcache_latency;
521
522 if (stall_ticks) {
523 Tick stall_cycles = stall_ticks / ticks(1);
524 Tick aligned_stall_ticks = ticks(stall_cycles);
525
526 if (aligned_stall_ticks < stall_ticks)
527 aligned_stall_ticks += 1;
528
529 latency += aligned_stall_ticks;
530 }
531
532 }
533 if(fault != NoFault || !stayAtPC)
534 advancePC(fault);
535 }
536
537 // instruction takes at least one cycle
538 if (latency < ticks(1))
539 latency = ticks(1);
540
541 if (_status != Idle)
542 schedule(tickEvent, curTick() + latency);
543}
544
545
546void
547AtomicSimpleCPU::printAddr(Addr a)
548{
549 dcachePort.printAddr(a);
550}
551
552
553////////////////////////////////////////////////////////////////////////
554//
555// AtomicSimpleCPU Simulation Object
556//
557AtomicSimpleCPU *
558AtomicSimpleCPUParams::create()
559{
560 numThreads = 1;
561 if (!FullSystem && workload.size() != 1)
562 panic("only one workload allowed");
563 return new AtomicSimpleCPU(this);
564}
| 487 else
488 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
489
490 assert(!ifetch_pkt.isError());
491
492 // ifetch_req is initialized to read the instruction directly
493 // into the CPU object's inst field.
494 //}
495 }
496
497 preExecute();
498
499 if (curStaticInst) {
500 fault = curStaticInst->execute(this, traceData);
501
502 // keep an instruction count
503 if (fault == NoFault)
504 countInst();
505 else if (traceData && !DTRACE(ExecFaulting)) {
506 delete traceData;
507 traceData = NULL;
508 }
509
510 postExecute();
511 }
512
513 // @todo remove me after debugging with legion done
514 if (curStaticInst && (!curStaticInst->isMicroop() ||
515 curStaticInst->isFirstMicroop()))
516 instCnt++;
517
518 Tick stall_ticks = 0;
519 if (simulate_inst_stalls && icache_access)
520 stall_ticks += icache_latency;
521
522 if (simulate_data_stalls && dcache_access)
523 stall_ticks += dcache_latency;
524
525 if (stall_ticks) {
526 Tick stall_cycles = stall_ticks / ticks(1);
527 Tick aligned_stall_ticks = ticks(stall_cycles);
528
529 if (aligned_stall_ticks < stall_ticks)
530 aligned_stall_ticks += 1;
531
532 latency += aligned_stall_ticks;
533 }
534
535 }
536 if(fault != NoFault || !stayAtPC)
537 advancePC(fault);
538 }
539
540 // instruction takes at least one cycle
541 if (latency < ticks(1))
542 latency = ticks(1);
543
544 if (_status != Idle)
545 schedule(tickEvent, curTick() + latency);
546}
547
548
549void
550AtomicSimpleCPU::printAddr(Addr a)
551{
552 dcachePort.printAddr(a);
553}
554
555
556////////////////////////////////////////////////////////////////////////
557//
558// AtomicSimpleCPU Simulation Object
559//
560AtomicSimpleCPU *
561AtomicSimpleCPUParams::create()
562{
563 numThreads = 1;
564 if (!FullSystem && workload.size() != 1)
565 panic("only one workload allowed");
566 return new AtomicSimpleCPU(this);
567}
|