1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/atomic.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "params/AtomicSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
46 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
47{
48}
49
50
51void
52AtomicSimpleCPU::TickEvent::process()
53{
54 cpu->tick();
55}
56
57const char *
58AtomicSimpleCPU::TickEvent::description()
59{
60 return "AtomicSimpleCPU tick";
61}
62
63Port *
64AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
65{
66 if (if_name == "dcache_port")
67 return &dcachePort;
68 else if (if_name == "icache_port")
69 return &icachePort;
70 else if (if_name == "physmem_port") {
71 hasPhysMemPort = true;
72 return &physmemPort;
73 }
74 else
75 panic("No Such Port\n");
76}
77
78void
79AtomicSimpleCPU::init()
80{
81 BaseCPU::init();
82#if FULL_SYSTEM
83 for (int i = 0; i < threadContexts.size(); ++i) {
84 ThreadContext *tc = threadContexts[i];
85
86 // initialize CPU, including PC
87 TheISA::initCPU(tc, tc->readCpuId());
88 }
89#endif
90 if (hasPhysMemPort) {
91 bool snoop = false;
92 AddrRangeList pmAddrList;
93 physmemPort.getPeerAddressRanges(pmAddrList, snoop);
94 physMemAddr = *pmAddrList.begin();
95 }
96}
97
98bool
99AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
100{
101 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
102 return true;
103}
104
105Tick
106AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
107{
108 //Snooping a coherence request, just return
109 return 0;
110}
111
112void
113AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
114{
115 //No internal storage to update, just return
116 return;
117}
118
119void
120AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
121{
122 if (status == RangeChange) {
123 if (!snoopRangeSent) {
124 snoopRangeSent = true;
125 sendStatusChange(Port::RangeChange);
126 }
127 return;
128 }
129
130 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
131}
132
133void
134AtomicSimpleCPU::CpuPort::recvRetry()
135{
136 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
137}
138
139void
140AtomicSimpleCPU::DcachePort::setPeer(Port *port)
141{
142 Port::setPeer(port);
143
144#if FULL_SYSTEM
145 // Update the ThreadContext's memory ports (Functional/Virtual
146 // Ports)
147 cpu->tcBase()->connectMemPorts();
148#endif
149}
150
151AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
152 : BaseSimpleCPU(p), tickEvent(this),
153 width(p->width), simulate_stalls(p->simulate_stalls),
154 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
155 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
156{
157 _status = Idle;
158
159 icachePort.snoopRangeSent = false;
160 dcachePort.snoopRangeSent = false;
161
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/atomic.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "params/AtomicSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
46 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
47{
48}
49
50
51void
52AtomicSimpleCPU::TickEvent::process()
53{
54 cpu->tick();
55}
56
57const char *
58AtomicSimpleCPU::TickEvent::description()
59{
60 return "AtomicSimpleCPU tick";
61}
62
63Port *
64AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
65{
66 if (if_name == "dcache_port")
67 return &dcachePort;
68 else if (if_name == "icache_port")
69 return &icachePort;
70 else if (if_name == "physmem_port") {
71 hasPhysMemPort = true;
72 return &physmemPort;
73 }
74 else
75 panic("No Such Port\n");
76}
77
78void
79AtomicSimpleCPU::init()
80{
81 BaseCPU::init();
82#if FULL_SYSTEM
83 for (int i = 0; i < threadContexts.size(); ++i) {
84 ThreadContext *tc = threadContexts[i];
85
86 // initialize CPU, including PC
87 TheISA::initCPU(tc, tc->readCpuId());
88 }
89#endif
90 if (hasPhysMemPort) {
91 bool snoop = false;
92 AddrRangeList pmAddrList;
93 physmemPort.getPeerAddressRanges(pmAddrList, snoop);
94 physMemAddr = *pmAddrList.begin();
95 }
96}
97
98bool
99AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
100{
101 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
102 return true;
103}
104
105Tick
106AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
107{
108 //Snooping a coherence request, just return
109 return 0;
110}
111
112void
113AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
114{
115 //No internal storage to update, just return
116 return;
117}
118
119void
120AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
121{
122 if (status == RangeChange) {
123 if (!snoopRangeSent) {
124 snoopRangeSent = true;
125 sendStatusChange(Port::RangeChange);
126 }
127 return;
128 }
129
130 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
131}
132
133void
134AtomicSimpleCPU::CpuPort::recvRetry()
135{
136 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
137}
138
139void
140AtomicSimpleCPU::DcachePort::setPeer(Port *port)
141{
142 Port::setPeer(port);
143
144#if FULL_SYSTEM
145 // Update the ThreadContext's memory ports (Functional/Virtual
146 // Ports)
147 cpu->tcBase()->connectMemPorts();
148#endif
149}
150
151AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
152 : BaseSimpleCPU(p), tickEvent(this),
153 width(p->width), simulate_stalls(p->simulate_stalls),
154 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
155 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
156{
157 _status = Idle;
158
159 icachePort.snoopRangeSent = false;
160 dcachePort.snoopRangeSent = false;
161
|
240}
241
242
243void
244AtomicSimpleCPU::activateContext(int thread_num, int delay)
245{
246 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
247
248 assert(thread_num == 0);
249 assert(thread);
250
251 assert(_status == Idle);
252 assert(!tickEvent.scheduled());
253
254 notIdleFraction++;
255 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
256
257 //Make sure ticks are still on multiples of cycles
258 tickEvent.schedule(nextCycle(curTick + ticks(delay)));
259 _status = Running;
260}
261
262
263void
264AtomicSimpleCPU::suspendContext(int thread_num)
265{
266 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
267
268 assert(thread_num == 0);
269 assert(thread);
270
271 assert(_status == Running);
272
273 // tick event may not be scheduled if this gets called from inside
274 // an instruction's execution, e.g. "quiesce"
275 if (tickEvent.scheduled())
276 tickEvent.deschedule();
277
278 notIdleFraction--;
279 _status = Idle;
280}
281
282
283template <class T>
284Fault
285AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
286{
287 // use the CPU's statically allocated read request and packet objects
288 Request *req = &data_read_req;
289
290 if (traceData) {
291 traceData->setAddr(addr);
292 }
293
294 //The block size of our peer.
295 int blockSize = dcachePort.peerBlockSize();
296 //The size of the data we're trying to read.
297 int dataSize = sizeof(T);
298
299 uint8_t * dataPtr = (uint8_t *)&data;
300
301 //The address of the second part of this access if it needs to be split
302 //across a cache line boundary.
303 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
304
305 if(secondAddr > addr)
306 dataSize = secondAddr - addr;
307
308 dcache_latency = 0;
309
310 while(1) {
311 req->setVirt(0, addr, dataSize, flags, thread->readPC());
312
313 // translate to physical address
314 Fault fault = thread->translateDataReadReq(req);
315
316 // Now do the access.
317 if (fault == NoFault) {
318 Packet pkt = Packet(req,
319 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
320 Packet::Broadcast);
321 pkt.dataStatic(dataPtr);
322
323 if (req->isMmapedIpr())
324 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
325 else {
326 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
327 dcache_latency += physmemPort.sendAtomic(&pkt);
328 else
329 dcache_latency += dcachePort.sendAtomic(&pkt);
330 }
331 dcache_access = true;
332
333 assert(!pkt.isError());
334
335 if (req->isLocked()) {
336 TheISA::handleLockedRead(thread, req);
337 }
338 }
339
340 // This will need a new way to tell if it has a dcache attached.
341 if (req->isUncacheable())
342 recordEvent("Uncached Read");
343
344 //If there's a fault, return it
345 if (fault != NoFault)
346 return fault;
347 //If we don't need to access a second cache line, stop now.
348 if (secondAddr <= addr)
349 {
350 data = gtoh(data);
351 return fault;
352 }
353
354 /*
355 * Set up for accessing the second cache line.
356 */
357
358 //Move the pointer we're reading into to the correct location.
359 dataPtr += dataSize;
360 //Adjust the size to get the remaining bytes.
361 dataSize = addr + sizeof(T) - secondAddr;
362 //And access the right address.
363 addr = secondAddr;
364 }
365}
366
367#ifndef DOXYGEN_SHOULD_SKIP_THIS
368
369template
370Fault
371AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
372
373template
374Fault
375AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
376
377template
378Fault
379AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
380
381template
382Fault
383AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
384
385template
386Fault
387AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
388
389template
390Fault
391AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
392
393#endif //DOXYGEN_SHOULD_SKIP_THIS
394
395template<>
396Fault
397AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
398{
399 return read(addr, *(uint64_t*)&data, flags);
400}
401
402template<>
403Fault
404AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
405{
406 return read(addr, *(uint32_t*)&data, flags);
407}
408
409
410template<>
411Fault
412AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
413{
414 return read(addr, (uint32_t&)data, flags);
415}
416
417
418template <class T>
419Fault
420AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
421{
422 // use the CPU's statically allocated write request and packet objects
423 Request *req = &data_write_req;
424
425 if (traceData) {
426 traceData->setAddr(addr);
427 }
428
429 //The block size of our peer.
430 int blockSize = dcachePort.peerBlockSize();
431 //The size of the data we're trying to read.
432 int dataSize = sizeof(T);
433
434 uint8_t * dataPtr = (uint8_t *)&data;
435
436 //The address of the second part of this access if it needs to be split
437 //across a cache line boundary.
438 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
439
440 if(secondAddr > addr)
441 dataSize = secondAddr - addr;
442
443 dcache_latency = 0;
444
445 while(1) {
446 req->setVirt(0, addr, dataSize, flags, thread->readPC());
447
448 // translate to physical address
449 Fault fault = thread->translateDataWriteReq(req);
450
451 // Now do the access.
452 if (fault == NoFault) {
453 MemCmd cmd = MemCmd::WriteReq; // default
454 bool do_access = true; // flag to suppress cache access
455
456 if (req->isLocked()) {
457 cmd = MemCmd::StoreCondReq;
458 do_access = TheISA::handleLockedWrite(thread, req);
459 } else if (req->isSwap()) {
460 cmd = MemCmd::SwapReq;
461 if (req->isCondSwap()) {
462 assert(res);
463 req->setExtraData(*res);
464 }
465 }
466
467 if (do_access) {
468 Packet pkt = Packet(req, cmd, Packet::Broadcast);
469 pkt.dataStatic(dataPtr);
470
471 if (req->isMmapedIpr()) {
472 dcache_latency +=
473 TheISA::handleIprWrite(thread->getTC(), &pkt);
474 } else {
475 //XXX This needs to be outside of the loop in order to
476 //work properly for cache line boundary crossing
477 //accesses in transendian simulations.
478 data = htog(data);
479 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
480 dcache_latency += physmemPort.sendAtomic(&pkt);
481 else
482 dcache_latency += dcachePort.sendAtomic(&pkt);
483 }
484 dcache_access = true;
485 assert(!pkt.isError());
486
487 if (req->isSwap()) {
488 assert(res);
489 *res = pkt.get<T>();
490 }
491 }
492
493 if (res && !req->isSwap()) {
494 *res = req->getExtraData();
495 }
496 }
497
498 // This will need a new way to tell if it's hooked up to a cache or not.
499 if (req->isUncacheable())
500 recordEvent("Uncached Write");
501
502 //If there's a fault or we don't need to access a second cache line,
503 //stop now.
504 if (fault != NoFault || secondAddr <= addr)
505 {
506 // If the write needs to have a fault on the access, consider
507 // calling changeStatus() and changing it to "bad addr write"
508 // or something.
509 return fault;
510 }
511
512 /*
513 * Set up for accessing the second cache line.
514 */
515
516 //Move the pointer we're reading into to the correct location.
517 dataPtr += dataSize;
518 //Adjust the size to get the remaining bytes.
519 dataSize = addr + sizeof(T) - secondAddr;
520 //And access the right address.
521 addr = secondAddr;
522 }
523}
524
525
526#ifndef DOXYGEN_SHOULD_SKIP_THIS
527
528template
529Fault
530AtomicSimpleCPU::write(Twin32_t data, Addr addr,
531 unsigned flags, uint64_t *res);
532
533template
534Fault
535AtomicSimpleCPU::write(Twin64_t data, Addr addr,
536 unsigned flags, uint64_t *res);
537
538template
539Fault
540AtomicSimpleCPU::write(uint64_t data, Addr addr,
541 unsigned flags, uint64_t *res);
542
543template
544Fault
545AtomicSimpleCPU::write(uint32_t data, Addr addr,
546 unsigned flags, uint64_t *res);
547
548template
549Fault
550AtomicSimpleCPU::write(uint16_t data, Addr addr,
551 unsigned flags, uint64_t *res);
552
553template
554Fault
555AtomicSimpleCPU::write(uint8_t data, Addr addr,
556 unsigned flags, uint64_t *res);
557
558#endif //DOXYGEN_SHOULD_SKIP_THIS
559
560template<>
561Fault
562AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
563{
564 return write(*(uint64_t*)&data, addr, flags, res);
565}
566
567template<>
568Fault
569AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
570{
571 return write(*(uint32_t*)&data, addr, flags, res);
572}
573
574
575template<>
576Fault
577AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
578{
579 return write((uint32_t)data, addr, flags, res);
580}
581
582
583void
584AtomicSimpleCPU::tick()
585{
586 DPRINTF(SimpleCPU, "Tick\n");
587
588 Tick latency = ticks(1); // instruction takes one cycle by default
589
590 for (int i = 0; i < width; ++i) {
591 numCycles++;
592
593 if (!curStaticInst || !curStaticInst->isDelayedCommit())
594 checkForInterrupts();
595
596 Fault fault = setupFetchRequest(&ifetch_req);
597
598 if (fault == NoFault) {
599 Tick icache_latency = 0;
600 bool icache_access = false;
601 dcache_access = false; // assume no dcache access
602
603 //Fetch more instruction memory if necessary
604 //if(predecoder.needMoreBytes())
605 //{
606 icache_access = true;
607 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
608 Packet::Broadcast);
609 ifetch_pkt.dataStatic(&inst);
610
611 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
612 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
613 else
614 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
615
616 assert(!ifetch_pkt.isError());
617
618 // ifetch_req is initialized to read the instruction directly
619 // into the CPU object's inst field.
620 //}
621
622 preExecute();
623
624 if (curStaticInst) {
625 fault = curStaticInst->execute(this, traceData);
626
627 // keep an instruction count
628 if (fault == NoFault)
629 countInst();
630 else if (traceData) {
631 // If there was a fault, we should trace this instruction.
632 delete traceData;
633 traceData = NULL;
634 }
635
636 postExecute();
637 }
638
639 // @todo remove me after debugging with legion done
640 if (curStaticInst && (!curStaticInst->isMicroop() ||
641 curStaticInst->isFirstMicroop()))
642 instCnt++;
643
644 if (simulate_stalls) {
645 Tick icache_stall =
646 icache_access ? icache_latency - ticks(1) : 0;
647 Tick dcache_stall =
648 dcache_access ? dcache_latency - ticks(1) : 0;
649 Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
650 if (ticks(stall_cycles) < (icache_stall + dcache_stall))
651 latency += ticks(stall_cycles+1);
652 else
653 latency += ticks(stall_cycles);
654 }
655
656 }
657 if(fault != NoFault || !stayAtPC)
658 advancePC(fault);
659 }
660
661 if (_status != Idle)
662 tickEvent.schedule(curTick + latency);
663}
664
665
666////////////////////////////////////////////////////////////////////////
667//
668// AtomicSimpleCPU Simulation Object
669//
670AtomicSimpleCPU *
671AtomicSimpleCPUParams::create()
672{
673 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
674 params->name = name;
675 params->numberOfThreads = 1;
676 params->max_insts_any_thread = max_insts_any_thread;
677 params->max_insts_all_threads = max_insts_all_threads;
678 params->max_loads_any_thread = max_loads_any_thread;
679 params->max_loads_all_threads = max_loads_all_threads;
680 params->progress_interval = progress_interval;
681 params->deferRegistration = defer_registration;
682 params->phase = phase;
683 params->clock = clock;
684 params->functionTrace = function_trace;
685 params->functionTraceStart = function_trace_start;
686 params->width = width;
687 params->simulate_stalls = simulate_stalls;
688 params->system = system;
689 params->cpu_id = cpu_id;
690 params->tracer = tracer;
691
692 params->itb = itb;
693 params->dtb = dtb;
694#if FULL_SYSTEM
695 params->profile = profile;
696 params->do_quiesce = do_quiesce;
697 params->do_checkpoint_insts = do_checkpoint_insts;
698 params->do_statistics_insts = do_statistics_insts;
699#else
700 if (workload.size() != 1)
701 panic("only one workload allowed");
702 params->process = workload[0];
703#endif
704
705 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
706 return cpu;
707}
| 242}
243
244
245void
246AtomicSimpleCPU::activateContext(int thread_num, int delay)
247{
248 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
249
250 assert(thread_num == 0);
251 assert(thread);
252
253 assert(_status == Idle);
254 assert(!tickEvent.scheduled());
255
256 notIdleFraction++;
257 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
258
259 //Make sure ticks are still on multiples of cycles
260 tickEvent.schedule(nextCycle(curTick + ticks(delay)));
261 _status = Running;
262}
263
264
265void
266AtomicSimpleCPU::suspendContext(int thread_num)
267{
268 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
269
270 assert(thread_num == 0);
271 assert(thread);
272
273 assert(_status == Running);
274
275 // tick event may not be scheduled if this gets called from inside
276 // an instruction's execution, e.g. "quiesce"
277 if (tickEvent.scheduled())
278 tickEvent.deschedule();
279
280 notIdleFraction--;
281 _status = Idle;
282}
283
284
285template <class T>
286Fault
287AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
288{
289 // use the CPU's statically allocated read request and packet objects
290 Request *req = &data_read_req;
291
292 if (traceData) {
293 traceData->setAddr(addr);
294 }
295
296 //The block size of our peer.
297 int blockSize = dcachePort.peerBlockSize();
298 //The size of the data we're trying to read.
299 int dataSize = sizeof(T);
300
301 uint8_t * dataPtr = (uint8_t *)&data;
302
303 //The address of the second part of this access if it needs to be split
304 //across a cache line boundary.
305 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
306
307 if(secondAddr > addr)
308 dataSize = secondAddr - addr;
309
310 dcache_latency = 0;
311
312 while(1) {
313 req->setVirt(0, addr, dataSize, flags, thread->readPC());
314
315 // translate to physical address
316 Fault fault = thread->translateDataReadReq(req);
317
318 // Now do the access.
319 if (fault == NoFault) {
320 Packet pkt = Packet(req,
321 req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
322 Packet::Broadcast);
323 pkt.dataStatic(dataPtr);
324
325 if (req->isMmapedIpr())
326 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
327 else {
328 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
329 dcache_latency += physmemPort.sendAtomic(&pkt);
330 else
331 dcache_latency += dcachePort.sendAtomic(&pkt);
332 }
333 dcache_access = true;
334
335 assert(!pkt.isError());
336
337 if (req->isLocked()) {
338 TheISA::handleLockedRead(thread, req);
339 }
340 }
341
342 // This will need a new way to tell if it has a dcache attached.
343 if (req->isUncacheable())
344 recordEvent("Uncached Read");
345
346 //If there's a fault, return it
347 if (fault != NoFault)
348 return fault;
349 //If we don't need to access a second cache line, stop now.
350 if (secondAddr <= addr)
351 {
352 data = gtoh(data);
353 return fault;
354 }
355
356 /*
357 * Set up for accessing the second cache line.
358 */
359
360 //Move the pointer we're reading into to the correct location.
361 dataPtr += dataSize;
362 //Adjust the size to get the remaining bytes.
363 dataSize = addr + sizeof(T) - secondAddr;
364 //And access the right address.
365 addr = secondAddr;
366 }
367}
368
369#ifndef DOXYGEN_SHOULD_SKIP_THIS
370
371template
372Fault
373AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
374
375template
376Fault
377AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
378
379template
380Fault
381AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
382
383template
384Fault
385AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
386
387template
388Fault
389AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
390
391template
392Fault
393AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
394
395#endif //DOXYGEN_SHOULD_SKIP_THIS
396
397template<>
398Fault
399AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
400{
401 return read(addr, *(uint64_t*)&data, flags);
402}
403
404template<>
405Fault
406AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
407{
408 return read(addr, *(uint32_t*)&data, flags);
409}
410
411
412template<>
413Fault
414AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
415{
416 return read(addr, (uint32_t&)data, flags);
417}
418
419
420template <class T>
421Fault
422AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
423{
424 // use the CPU's statically allocated write request and packet objects
425 Request *req = &data_write_req;
426
427 if (traceData) {
428 traceData->setAddr(addr);
429 }
430
431 //The block size of our peer.
432 int blockSize = dcachePort.peerBlockSize();
433 //The size of the data we're trying to read.
434 int dataSize = sizeof(T);
435
436 uint8_t * dataPtr = (uint8_t *)&data;
437
438 //The address of the second part of this access if it needs to be split
439 //across a cache line boundary.
440 Addr secondAddr = roundDown(addr + dataSize - 1, blockSize);
441
442 if(secondAddr > addr)
443 dataSize = secondAddr - addr;
444
445 dcache_latency = 0;
446
447 while(1) {
448 req->setVirt(0, addr, dataSize, flags, thread->readPC());
449
450 // translate to physical address
451 Fault fault = thread->translateDataWriteReq(req);
452
453 // Now do the access.
454 if (fault == NoFault) {
455 MemCmd cmd = MemCmd::WriteReq; // default
456 bool do_access = true; // flag to suppress cache access
457
458 if (req->isLocked()) {
459 cmd = MemCmd::StoreCondReq;
460 do_access = TheISA::handleLockedWrite(thread, req);
461 } else if (req->isSwap()) {
462 cmd = MemCmd::SwapReq;
463 if (req->isCondSwap()) {
464 assert(res);
465 req->setExtraData(*res);
466 }
467 }
468
469 if (do_access) {
470 Packet pkt = Packet(req, cmd, Packet::Broadcast);
471 pkt.dataStatic(dataPtr);
472
473 if (req->isMmapedIpr()) {
474 dcache_latency +=
475 TheISA::handleIprWrite(thread->getTC(), &pkt);
476 } else {
477 //XXX This needs to be outside of the loop in order to
478 //work properly for cache line boundary crossing
479 //accesses in transendian simulations.
480 data = htog(data);
481 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
482 dcache_latency += physmemPort.sendAtomic(&pkt);
483 else
484 dcache_latency += dcachePort.sendAtomic(&pkt);
485 }
486 dcache_access = true;
487 assert(!pkt.isError());
488
489 if (req->isSwap()) {
490 assert(res);
491 *res = pkt.get<T>();
492 }
493 }
494
495 if (res && !req->isSwap()) {
496 *res = req->getExtraData();
497 }
498 }
499
500 // This will need a new way to tell if it's hooked up to a cache or not.
501 if (req->isUncacheable())
502 recordEvent("Uncached Write");
503
504 //If there's a fault or we don't need to access a second cache line,
505 //stop now.
506 if (fault != NoFault || secondAddr <= addr)
507 {
508 // If the write needs to have a fault on the access, consider
509 // calling changeStatus() and changing it to "bad addr write"
510 // or something.
511 return fault;
512 }
513
514 /*
515 * Set up for accessing the second cache line.
516 */
517
518 //Move the pointer we're reading into to the correct location.
519 dataPtr += dataSize;
520 //Adjust the size to get the remaining bytes.
521 dataSize = addr + sizeof(T) - secondAddr;
522 //And access the right address.
523 addr = secondAddr;
524 }
525}
526
527
528#ifndef DOXYGEN_SHOULD_SKIP_THIS
529
530template
531Fault
532AtomicSimpleCPU::write(Twin32_t data, Addr addr,
533 unsigned flags, uint64_t *res);
534
535template
536Fault
537AtomicSimpleCPU::write(Twin64_t data, Addr addr,
538 unsigned flags, uint64_t *res);
539
540template
541Fault
542AtomicSimpleCPU::write(uint64_t data, Addr addr,
543 unsigned flags, uint64_t *res);
544
545template
546Fault
547AtomicSimpleCPU::write(uint32_t data, Addr addr,
548 unsigned flags, uint64_t *res);
549
550template
551Fault
552AtomicSimpleCPU::write(uint16_t data, Addr addr,
553 unsigned flags, uint64_t *res);
554
555template
556Fault
557AtomicSimpleCPU::write(uint8_t data, Addr addr,
558 unsigned flags, uint64_t *res);
559
560#endif //DOXYGEN_SHOULD_SKIP_THIS
561
562template<>
563Fault
564AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
565{
566 return write(*(uint64_t*)&data, addr, flags, res);
567}
568
569template<>
570Fault
571AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
572{
573 return write(*(uint32_t*)&data, addr, flags, res);
574}
575
576
577template<>
578Fault
579AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
580{
581 return write((uint32_t)data, addr, flags, res);
582}
583
584
585void
586AtomicSimpleCPU::tick()
587{
588 DPRINTF(SimpleCPU, "Tick\n");
589
590 Tick latency = ticks(1); // instruction takes one cycle by default
591
592 for (int i = 0; i < width; ++i) {
593 numCycles++;
594
595 if (!curStaticInst || !curStaticInst->isDelayedCommit())
596 checkForInterrupts();
597
598 Fault fault = setupFetchRequest(&ifetch_req);
599
600 if (fault == NoFault) {
601 Tick icache_latency = 0;
602 bool icache_access = false;
603 dcache_access = false; // assume no dcache access
604
605 //Fetch more instruction memory if necessary
606 //if(predecoder.needMoreBytes())
607 //{
608 icache_access = true;
609 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
610 Packet::Broadcast);
611 ifetch_pkt.dataStatic(&inst);
612
613 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
614 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
615 else
616 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
617
618 assert(!ifetch_pkt.isError());
619
620 // ifetch_req is initialized to read the instruction directly
621 // into the CPU object's inst field.
622 //}
623
624 preExecute();
625
626 if (curStaticInst) {
627 fault = curStaticInst->execute(this, traceData);
628
629 // keep an instruction count
630 if (fault == NoFault)
631 countInst();
632 else if (traceData) {
633 // If there was a fault, we should trace this instruction.
634 delete traceData;
635 traceData = NULL;
636 }
637
638 postExecute();
639 }
640
641 // @todo remove me after debugging with legion done
642 if (curStaticInst && (!curStaticInst->isMicroop() ||
643 curStaticInst->isFirstMicroop()))
644 instCnt++;
645
646 if (simulate_stalls) {
647 Tick icache_stall =
648 icache_access ? icache_latency - ticks(1) : 0;
649 Tick dcache_stall =
650 dcache_access ? dcache_latency - ticks(1) : 0;
651 Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
652 if (ticks(stall_cycles) < (icache_stall + dcache_stall))
653 latency += ticks(stall_cycles+1);
654 else
655 latency += ticks(stall_cycles);
656 }
657
658 }
659 if(fault != NoFault || !stayAtPC)
660 advancePC(fault);
661 }
662
663 if (_status != Idle)
664 tickEvent.schedule(curTick + latency);
665}
666
667
668////////////////////////////////////////////////////////////////////////
669//
670// AtomicSimpleCPU Simulation Object
671//
672AtomicSimpleCPU *
673AtomicSimpleCPUParams::create()
674{
675 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
676 params->name = name;
677 params->numberOfThreads = 1;
678 params->max_insts_any_thread = max_insts_any_thread;
679 params->max_insts_all_threads = max_insts_all_threads;
680 params->max_loads_any_thread = max_loads_any_thread;
681 params->max_loads_all_threads = max_loads_all_threads;
682 params->progress_interval = progress_interval;
683 params->deferRegistration = defer_registration;
684 params->phase = phase;
685 params->clock = clock;
686 params->functionTrace = function_trace;
687 params->functionTraceStart = function_trace_start;
688 params->width = width;
689 params->simulate_stalls = simulate_stalls;
690 params->system = system;
691 params->cpu_id = cpu_id;
692 params->tracer = tracer;
693
694 params->itb = itb;
695 params->dtb = dtb;
696#if FULL_SYSTEM
697 params->profile = profile;
698 params->do_quiesce = do_quiesce;
699 params->do_checkpoint_insts = do_checkpoint_insts;
700 params->do_statistics_insts = do_statistics_insts;
701#else
702 if (workload.size() != 1)
703 panic("only one workload allowed");
704 params->process = workload[0];
705#endif
706
707 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
708 return cpu;
709}
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