1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/atomic.hh"
35#include "mem/packet.hh"
36#include "mem/packet_access.hh"
37#include "sim/builder.hh"
38#include "sim/system.hh"
39
40using namespace std;
41using namespace TheISA;
42
43AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
44 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
45{
46}
47
48
49void
50AtomicSimpleCPU::TickEvent::process()
51{
52 cpu->tick();
53}
54
55const char *
56AtomicSimpleCPU::TickEvent::description()
57{
58 return "AtomicSimpleCPU tick event";
59}
60
61Port *
62AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
63{
64 if (if_name == "dcache_port")
65 return &dcachePort;
66 else if (if_name == "icache_port")
67 return &icachePort;
68 else
69 panic("No Such Port\n");
70}
71
72void
73AtomicSimpleCPU::init()
74{
75 //Create Memory Ports (conect them up)
76// Port *mem_dport = mem->getPort("");
77// dcachePort.setPeer(mem_dport);
78// mem_dport->setPeer(&dcachePort);
79
80// Port *mem_iport = mem->getPort("");
81// icachePort.setPeer(mem_iport);
82// mem_iport->setPeer(&icachePort);
83
84 BaseCPU::init();
85#if FULL_SYSTEM
86 for (int i = 0; i < threadContexts.size(); ++i) {
87 ThreadContext *tc = threadContexts[i];
88
89 // initialize CPU, including PC
90 TheISA::initCPU(tc, tc->readCpuId());
91 }
92#endif
93}
94
95bool
96AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
97{
98 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
99 return true;
100}
101
102Tick
103AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
104{
105 //Snooping a coherence request, just return
106 return curTick;
107}
108
109void
110AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
111{
112 //No internal storage to update, just return
113 return;
114}
115
116void
117AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
118{
119 if (status == RangeChange)
120 return;
121
122 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
123}
124
125void
126AtomicSimpleCPU::CpuPort::recvRetry()
127{
128 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
129}
130
131
132AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
133 : BaseSimpleCPU(p), tickEvent(this),
134 width(p->width), simulate_stalls(p->simulate_stalls),
135 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
136{
137 _status = Idle;
138
139 ifetch_req = new Request();
140 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
141 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
142 ifetch_pkt->dataStatic(&inst);
143
144 data_read_req = new Request();
145 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
146 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
147 Packet::Broadcast);
148 data_read_pkt->dataStatic(&dataReg);
149
150 data_write_req = new Request();
151 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
152 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
153 Packet::Broadcast);
154}
155
156
157AtomicSimpleCPU::~AtomicSimpleCPU()
158{
159}
160
161void
162AtomicSimpleCPU::serialize(ostream &os)
163{
164 SimObject::State so_state = SimObject::getState();
165 SERIALIZE_ENUM(so_state);
166 Status _status = status();
167 SERIALIZE_ENUM(_status);
168 BaseSimpleCPU::serialize(os);
169 nameOut(os, csprintf("%s.tickEvent", name()));
170 tickEvent.serialize(os);
171}
172
173void
174AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
175{
176 SimObject::State so_state;
177 UNSERIALIZE_ENUM(so_state);
178 UNSERIALIZE_ENUM(_status);
179 BaseSimpleCPU::unserialize(cp, section);
180 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
181}
182
183void
184AtomicSimpleCPU::resume()
185{
186 if (_status != SwitchedOut && _status != Idle) {
187 assert(system->getMemoryMode() == System::Atomic);
188
189 changeState(SimObject::Running);
190 if (thread->status() == ThreadContext::Active) {
191 if (!tickEvent.scheduled()) {
192 Tick nextTick = curTick + cycles(1) - 1;
193 nextTick -= (nextTick % (cycles(1)));
194 tickEvent.schedule(nextTick);
195 }
196 }
197 }
198}
199
200void
201AtomicSimpleCPU::switchOut()
202{
203 assert(status() == Running || status() == Idle);
204 _status = SwitchedOut;
205
206 tickEvent.squash();
207}
208
209
210void
211AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
212{
213 BaseCPU::takeOverFrom(oldCPU);
214
215 assert(!tickEvent.scheduled());
216
217 // if any of this CPU's ThreadContexts are active, mark the CPU as
218 // running and schedule its tick event.
219 for (int i = 0; i < threadContexts.size(); ++i) {
220 ThreadContext *tc = threadContexts[i];
221 if (tc->status() == ThreadContext::Active && _status != Running) {
222 _status = Running;
223 Tick nextTick = curTick + cycles(1) - 1;
224 nextTick -= (nextTick % (cycles(1)));
225 tickEvent.schedule(nextTick);
226 break;
227 }
228 }
229}
230
231
232void
233AtomicSimpleCPU::activateContext(int thread_num, int delay)
234{
235 assert(thread_num == 0);
236 assert(thread);
237
238 assert(_status == Idle);
239 assert(!tickEvent.scheduled());
240
241 notIdleFraction++;
242 //Make sure ticks are still on multiples of cycles
243 Tick nextTick = curTick + cycles(delay + 1) - 1;
244 nextTick -= (nextTick % (cycles(1)));
245 tickEvent.schedule(nextTick);
246 _status = Running;
247}
248
249
250void
251AtomicSimpleCPU::suspendContext(int thread_num)
252{
253 assert(thread_num == 0);
254 assert(thread);
255
256 assert(_status == Running);
257
258 // tick event may not be scheduled if this gets called from inside
259 // an instruction's execution, e.g. "quiesce"
260 if (tickEvent.scheduled())
261 tickEvent.deschedule();
262
263 notIdleFraction--;
264 _status = Idle;
265}
266
267
268template <class T>
269Fault
270AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
271{
272 // use the CPU's statically allocated read request and packet objects
273 Request *req = data_read_req;
274 PacketPtr pkt = data_read_pkt;
275
276 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
277
278 if (traceData) {
279 traceData->setAddr(addr);
280 }
281
282 // translate to physical address
283 Fault fault = thread->translateDataReadReq(req);
284
285 // Now do the access.
286 if (fault == NoFault) {
287 pkt->reinitFromRequest();
288
289 dcache_latency = dcachePort.sendAtomic(pkt);
290 dcache_access = true;
291
292 assert(pkt->result == Packet::Success);
293 data = pkt->get<T>();
294
295 if (req->isLocked()) {
296 TheISA::handleLockedRead(thread, req);
297 }
298 }
299
300 // This will need a new way to tell if it has a dcache attached.
301 if (req->isUncacheable())
302 recordEvent("Uncached Read");
303
304 return fault;
305}
306
307#ifndef DOXYGEN_SHOULD_SKIP_THIS
308
309template
310Fault
311AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
312
313template
314Fault
315AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
316
317template
318Fault
319AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
320
321template
322Fault
323AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
324
325#endif //DOXYGEN_SHOULD_SKIP_THIS
326
327template<>
328Fault
329AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
330{
331 return read(addr, *(uint64_t*)&data, flags);
332}
333
334template<>
335Fault
336AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
337{
338 return read(addr, *(uint32_t*)&data, flags);
339}
340
341
342template<>
343Fault
344AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
345{
346 return read(addr, (uint32_t&)data, flags);
347}
348
349
350template <class T>
351Fault
352AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
353{
354 // use the CPU's statically allocated write request and packet objects
355 Request *req = data_write_req;
356 PacketPtr pkt = data_write_pkt;
357
358 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
359
360 if (traceData) {
361 traceData->setAddr(addr);
362 }
363
364 // translate to physical address
365 Fault fault = thread->translateDataWriteReq(req);
366
367 // Now do the access.
368 if (fault == NoFault) {
369 bool do_access = true; // flag to suppress cache access
370
371 if (req->isLocked()) {
372 do_access = TheISA::handleLockedWrite(thread, req);
373 }
374
375 if (do_access) {
376 data = htog(data);
377 pkt->reinitFromRequest();
378 pkt->dataStatic(&data);
379
380 dcache_latency = dcachePort.sendAtomic(pkt);
381 dcache_access = true;
382
383 assert(pkt->result == Packet::Success);
384 }
385
386 if (req->isLocked()) {
387 uint64_t scResult = req->getScResult();
388 if (scResult != 0) {
389 // clear failure counter
390 thread->setStCondFailures(0);
391 }
392 if (res) {
393 *res = req->getScResult();
394 }
395 }
396 }
397
398 // This will need a new way to tell if it's hooked up to a cache or not.
399 if (req->isUncacheable())
400 recordEvent("Uncached Write");
401
402 // If the write needs to have a fault on the access, consider calling
403 // changeStatus() and changing it to "bad addr write" or something.
404 return fault;
405}
406
407
408#ifndef DOXYGEN_SHOULD_SKIP_THIS
409template
410Fault
411AtomicSimpleCPU::write(uint64_t data, Addr addr,
412 unsigned flags, uint64_t *res);
413
414template
415Fault
416AtomicSimpleCPU::write(uint32_t data, Addr addr,
417 unsigned flags, uint64_t *res);
418
419template
420Fault
421AtomicSimpleCPU::write(uint16_t data, Addr addr,
422 unsigned flags, uint64_t *res);
423
424template
425Fault
426AtomicSimpleCPU::write(uint8_t data, Addr addr,
427 unsigned flags, uint64_t *res);
428
429#endif //DOXYGEN_SHOULD_SKIP_THIS
430
431template<>
432Fault
433AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
434{
435 return write(*(uint64_t*)&data, addr, flags, res);
436}
437
438template<>
439Fault
440AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
441{
442 return write(*(uint32_t*)&data, addr, flags, res);
443}
444
445
446template<>
447Fault
448AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
449{
450 return write((uint32_t)data, addr, flags, res);
451}
452
453
454void
455AtomicSimpleCPU::tick()
456{
457 Tick latency = cycles(1); // instruction takes one cycle by default
458
459 for (int i = 0; i < width; ++i) {
460 numCycles++;
461
462 if (!curStaticInst || !curStaticInst->isDelayedCommit())
463 checkForInterrupts();
464
465 Fault fault = setupFetchRequest(ifetch_req);
466
467 if (fault == NoFault) {
468 ifetch_pkt->reinitFromRequest();
469
470 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
471 // ifetch_req is initialized to read the instruction directly
472 // into the CPU object's inst field.
473
474 dcache_access = false; // assume no dcache access
475 preExecute();
476 fault = curStaticInst->execute(this, traceData);
477 postExecute();
478
479 if (simulate_stalls) {
480 Tick icache_stall = icache_latency - cycles(1);
481 Tick dcache_stall =
482 dcache_access ? dcache_latency - cycles(1) : 0;
483 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
484 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
485 latency += cycles(stall_cycles+1);
486 else
487 latency += cycles(stall_cycles);
488 }
489
490 }
491
492 advancePC(fault);
493 }
494
495 if (_status != Idle)
496 tickEvent.schedule(curTick + latency);
497}
498
499
500////////////////////////////////////////////////////////////////////////
501//
502// AtomicSimpleCPU Simulation Object
503//
504BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
505
506 Param<Counter> max_insts_any_thread;
507 Param<Counter> max_insts_all_threads;
508 Param<Counter> max_loads_any_thread;
509 Param<Counter> max_loads_all_threads;
510 Param<Tick> progress_interval;
511 SimObjectParam<MemObject *> mem;
512 SimObjectParam<System *> system;
513 Param<int> cpu_id;
514
515#if FULL_SYSTEM
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/atomic.hh"
35#include "mem/packet.hh"
36#include "mem/packet_access.hh"
37#include "sim/builder.hh"
38#include "sim/system.hh"
39
40using namespace std;
41using namespace TheISA;
42
43AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
44 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
45{
46}
47
48
49void
50AtomicSimpleCPU::TickEvent::process()
51{
52 cpu->tick();
53}
54
55const char *
56AtomicSimpleCPU::TickEvent::description()
57{
58 return "AtomicSimpleCPU tick event";
59}
60
61Port *
62AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
63{
64 if (if_name == "dcache_port")
65 return &dcachePort;
66 else if (if_name == "icache_port")
67 return &icachePort;
68 else
69 panic("No Such Port\n");
70}
71
72void
73AtomicSimpleCPU::init()
74{
75 //Create Memory Ports (conect them up)
76// Port *mem_dport = mem->getPort("");
77// dcachePort.setPeer(mem_dport);
78// mem_dport->setPeer(&dcachePort);
79
80// Port *mem_iport = mem->getPort("");
81// icachePort.setPeer(mem_iport);
82// mem_iport->setPeer(&icachePort);
83
84 BaseCPU::init();
85#if FULL_SYSTEM
86 for (int i = 0; i < threadContexts.size(); ++i) {
87 ThreadContext *tc = threadContexts[i];
88
89 // initialize CPU, including PC
90 TheISA::initCPU(tc, tc->readCpuId());
91 }
92#endif
93}
94
95bool
96AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
97{
98 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
99 return true;
100}
101
102Tick
103AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
104{
105 //Snooping a coherence request, just return
106 return curTick;
107}
108
109void
110AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
111{
112 //No internal storage to update, just return
113 return;
114}
115
116void
117AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
118{
119 if (status == RangeChange)
120 return;
121
122 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
123}
124
125void
126AtomicSimpleCPU::CpuPort::recvRetry()
127{
128 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
129}
130
131
132AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
133 : BaseSimpleCPU(p), tickEvent(this),
134 width(p->width), simulate_stalls(p->simulate_stalls),
135 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
136{
137 _status = Idle;
138
139 ifetch_req = new Request();
140 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
141 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
142 ifetch_pkt->dataStatic(&inst);
143
144 data_read_req = new Request();
145 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
146 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
147 Packet::Broadcast);
148 data_read_pkt->dataStatic(&dataReg);
149
150 data_write_req = new Request();
151 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
152 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
153 Packet::Broadcast);
154}
155
156
157AtomicSimpleCPU::~AtomicSimpleCPU()
158{
159}
160
161void
162AtomicSimpleCPU::serialize(ostream &os)
163{
164 SimObject::State so_state = SimObject::getState();
165 SERIALIZE_ENUM(so_state);
166 Status _status = status();
167 SERIALIZE_ENUM(_status);
168 BaseSimpleCPU::serialize(os);
169 nameOut(os, csprintf("%s.tickEvent", name()));
170 tickEvent.serialize(os);
171}
172
173void
174AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
175{
176 SimObject::State so_state;
177 UNSERIALIZE_ENUM(so_state);
178 UNSERIALIZE_ENUM(_status);
179 BaseSimpleCPU::unserialize(cp, section);
180 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
181}
182
183void
184AtomicSimpleCPU::resume()
185{
186 if (_status != SwitchedOut && _status != Idle) {
187 assert(system->getMemoryMode() == System::Atomic);
188
189 changeState(SimObject::Running);
190 if (thread->status() == ThreadContext::Active) {
191 if (!tickEvent.scheduled()) {
192 Tick nextTick = curTick + cycles(1) - 1;
193 nextTick -= (nextTick % (cycles(1)));
194 tickEvent.schedule(nextTick);
195 }
196 }
197 }
198}
199
200void
201AtomicSimpleCPU::switchOut()
202{
203 assert(status() == Running || status() == Idle);
204 _status = SwitchedOut;
205
206 tickEvent.squash();
207}
208
209
210void
211AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
212{
213 BaseCPU::takeOverFrom(oldCPU);
214
215 assert(!tickEvent.scheduled());
216
217 // if any of this CPU's ThreadContexts are active, mark the CPU as
218 // running and schedule its tick event.
219 for (int i = 0; i < threadContexts.size(); ++i) {
220 ThreadContext *tc = threadContexts[i];
221 if (tc->status() == ThreadContext::Active && _status != Running) {
222 _status = Running;
223 Tick nextTick = curTick + cycles(1) - 1;
224 nextTick -= (nextTick % (cycles(1)));
225 tickEvent.schedule(nextTick);
226 break;
227 }
228 }
229}
230
231
232void
233AtomicSimpleCPU::activateContext(int thread_num, int delay)
234{
235 assert(thread_num == 0);
236 assert(thread);
237
238 assert(_status == Idle);
239 assert(!tickEvent.scheduled());
240
241 notIdleFraction++;
242 //Make sure ticks are still on multiples of cycles
243 Tick nextTick = curTick + cycles(delay + 1) - 1;
244 nextTick -= (nextTick % (cycles(1)));
245 tickEvent.schedule(nextTick);
246 _status = Running;
247}
248
249
250void
251AtomicSimpleCPU::suspendContext(int thread_num)
252{
253 assert(thread_num == 0);
254 assert(thread);
255
256 assert(_status == Running);
257
258 // tick event may not be scheduled if this gets called from inside
259 // an instruction's execution, e.g. "quiesce"
260 if (tickEvent.scheduled())
261 tickEvent.deschedule();
262
263 notIdleFraction--;
264 _status = Idle;
265}
266
267
268template <class T>
269Fault
270AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
271{
272 // use the CPU's statically allocated read request and packet objects
273 Request *req = data_read_req;
274 PacketPtr pkt = data_read_pkt;
275
276 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
277
278 if (traceData) {
279 traceData->setAddr(addr);
280 }
281
282 // translate to physical address
283 Fault fault = thread->translateDataReadReq(req);
284
285 // Now do the access.
286 if (fault == NoFault) {
287 pkt->reinitFromRequest();
288
289 dcache_latency = dcachePort.sendAtomic(pkt);
290 dcache_access = true;
291
292 assert(pkt->result == Packet::Success);
293 data = pkt->get<T>();
294
295 if (req->isLocked()) {
296 TheISA::handleLockedRead(thread, req);
297 }
298 }
299
300 // This will need a new way to tell if it has a dcache attached.
301 if (req->isUncacheable())
302 recordEvent("Uncached Read");
303
304 return fault;
305}
306
307#ifndef DOXYGEN_SHOULD_SKIP_THIS
308
309template
310Fault
311AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
312
313template
314Fault
315AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
316
317template
318Fault
319AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
320
321template
322Fault
323AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
324
325#endif //DOXYGEN_SHOULD_SKIP_THIS
326
327template<>
328Fault
329AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
330{
331 return read(addr, *(uint64_t*)&data, flags);
332}
333
334template<>
335Fault
336AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
337{
338 return read(addr, *(uint32_t*)&data, flags);
339}
340
341
342template<>
343Fault
344AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
345{
346 return read(addr, (uint32_t&)data, flags);
347}
348
349
350template <class T>
351Fault
352AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
353{
354 // use the CPU's statically allocated write request and packet objects
355 Request *req = data_write_req;
356 PacketPtr pkt = data_write_pkt;
357
358 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
359
360 if (traceData) {
361 traceData->setAddr(addr);
362 }
363
364 // translate to physical address
365 Fault fault = thread->translateDataWriteReq(req);
366
367 // Now do the access.
368 if (fault == NoFault) {
369 bool do_access = true; // flag to suppress cache access
370
371 if (req->isLocked()) {
372 do_access = TheISA::handleLockedWrite(thread, req);
373 }
374
375 if (do_access) {
376 data = htog(data);
377 pkt->reinitFromRequest();
378 pkt->dataStatic(&data);
379
380 dcache_latency = dcachePort.sendAtomic(pkt);
381 dcache_access = true;
382
383 assert(pkt->result == Packet::Success);
384 }
385
386 if (req->isLocked()) {
387 uint64_t scResult = req->getScResult();
388 if (scResult != 0) {
389 // clear failure counter
390 thread->setStCondFailures(0);
391 }
392 if (res) {
393 *res = req->getScResult();
394 }
395 }
396 }
397
398 // This will need a new way to tell if it's hooked up to a cache or not.
399 if (req->isUncacheable())
400 recordEvent("Uncached Write");
401
402 // If the write needs to have a fault on the access, consider calling
403 // changeStatus() and changing it to "bad addr write" or something.
404 return fault;
405}
406
407
408#ifndef DOXYGEN_SHOULD_SKIP_THIS
409template
410Fault
411AtomicSimpleCPU::write(uint64_t data, Addr addr,
412 unsigned flags, uint64_t *res);
413
414template
415Fault
416AtomicSimpleCPU::write(uint32_t data, Addr addr,
417 unsigned flags, uint64_t *res);
418
419template
420Fault
421AtomicSimpleCPU::write(uint16_t data, Addr addr,
422 unsigned flags, uint64_t *res);
423
424template
425Fault
426AtomicSimpleCPU::write(uint8_t data, Addr addr,
427 unsigned flags, uint64_t *res);
428
429#endif //DOXYGEN_SHOULD_SKIP_THIS
430
431template<>
432Fault
433AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
434{
435 return write(*(uint64_t*)&data, addr, flags, res);
436}
437
438template<>
439Fault
440AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
441{
442 return write(*(uint32_t*)&data, addr, flags, res);
443}
444
445
446template<>
447Fault
448AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
449{
450 return write((uint32_t)data, addr, flags, res);
451}
452
453
454void
455AtomicSimpleCPU::tick()
456{
457 Tick latency = cycles(1); // instruction takes one cycle by default
458
459 for (int i = 0; i < width; ++i) {
460 numCycles++;
461
462 if (!curStaticInst || !curStaticInst->isDelayedCommit())
463 checkForInterrupts();
464
465 Fault fault = setupFetchRequest(ifetch_req);
466
467 if (fault == NoFault) {
468 ifetch_pkt->reinitFromRequest();
469
470 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
471 // ifetch_req is initialized to read the instruction directly
472 // into the CPU object's inst field.
473
474 dcache_access = false; // assume no dcache access
475 preExecute();
476 fault = curStaticInst->execute(this, traceData);
477 postExecute();
478
479 if (simulate_stalls) {
480 Tick icache_stall = icache_latency - cycles(1);
481 Tick dcache_stall =
482 dcache_access ? dcache_latency - cycles(1) : 0;
483 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
484 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
485 latency += cycles(stall_cycles+1);
486 else
487 latency += cycles(stall_cycles);
488 }
489
490 }
491
492 advancePC(fault);
493 }
494
495 if (_status != Idle)
496 tickEvent.schedule(curTick + latency);
497}
498
499
500////////////////////////////////////////////////////////////////////////
501//
502// AtomicSimpleCPU Simulation Object
503//
504BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
505
506 Param<Counter> max_insts_any_thread;
507 Param<Counter> max_insts_all_threads;
508 Param<Counter> max_loads_any_thread;
509 Param<Counter> max_loads_all_threads;
510 Param<Tick> progress_interval;
511 SimObjectParam<MemObject *> mem;
512 SimObjectParam<System *> system;
513 Param<int> cpu_id;
514
515#if FULL_SYSTEM
|
518 Param<Tick> profile;
519#else
520 SimObjectParam<Process *> workload;
521#endif // FULL_SYSTEM
522
523 Param<int> clock;
524
525 Param<bool> defer_registration;
526 Param<int> width;
527 Param<bool> function_trace;
528 Param<Tick> function_trace_start;
529 Param<bool> simulate_stalls;
530
531END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
532
533BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
534
535 INIT_PARAM(max_insts_any_thread,
536 "terminate when any thread reaches this inst count"),
537 INIT_PARAM(max_insts_all_threads,
538 "terminate when all threads have reached this inst count"),
539 INIT_PARAM(max_loads_any_thread,
540 "terminate when any thread reaches this load count"),
541 INIT_PARAM(max_loads_all_threads,
542 "terminate when all threads have reached this load count"),
543 INIT_PARAM(progress_interval, "Progress interval"),
544 INIT_PARAM(mem, "memory"),
545 INIT_PARAM(system, "system object"),
546 INIT_PARAM(cpu_id, "processor ID"),
547
548#if FULL_SYSTEM
549 INIT_PARAM(itb, "Instruction TLB"),
550 INIT_PARAM(dtb, "Data TLB"),
551 INIT_PARAM(profile, ""),
552#else
553 INIT_PARAM(workload, "processes to run"),
554#endif // FULL_SYSTEM
555
556 INIT_PARAM(clock, "clock speed"),
557 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
558 INIT_PARAM(width, "cpu width"),
559 INIT_PARAM(function_trace, "Enable function trace"),
560 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
561 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
562
563END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
564
565
566CREATE_SIM_OBJECT(AtomicSimpleCPU)
567{
568 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
569 params->name = getInstanceName();
570 params->numberOfThreads = 1;
571 params->max_insts_any_thread = max_insts_any_thread;
572 params->max_insts_all_threads = max_insts_all_threads;
573 params->max_loads_any_thread = max_loads_any_thread;
574 params->max_loads_all_threads = max_loads_all_threads;
575 params->progress_interval = progress_interval;
576 params->deferRegistration = defer_registration;
577 params->clock = clock;
578 params->functionTrace = function_trace;
579 params->functionTraceStart = function_trace_start;
580 params->width = width;
581 params->simulate_stalls = simulate_stalls;
582 params->mem = mem;
583 params->system = system;
584 params->cpu_id = cpu_id;
585
586#if FULL_SYSTEM
587 params->itb = itb;
588 params->dtb = dtb;
589 params->profile = profile;
590#else
591 params->process = workload;
592#endif
593
594 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
595 return cpu;
596}
597
598REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
599
| 518 Param<Tick> profile;
519#else
520 SimObjectParam<Process *> workload;
521#endif // FULL_SYSTEM
522
523 Param<int> clock;
524
525 Param<bool> defer_registration;
526 Param<int> width;
527 Param<bool> function_trace;
528 Param<Tick> function_trace_start;
529 Param<bool> simulate_stalls;
530
531END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
532
533BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
534
535 INIT_PARAM(max_insts_any_thread,
536 "terminate when any thread reaches this inst count"),
537 INIT_PARAM(max_insts_all_threads,
538 "terminate when all threads have reached this inst count"),
539 INIT_PARAM(max_loads_any_thread,
540 "terminate when any thread reaches this load count"),
541 INIT_PARAM(max_loads_all_threads,
542 "terminate when all threads have reached this load count"),
543 INIT_PARAM(progress_interval, "Progress interval"),
544 INIT_PARAM(mem, "memory"),
545 INIT_PARAM(system, "system object"),
546 INIT_PARAM(cpu_id, "processor ID"),
547
548#if FULL_SYSTEM
549 INIT_PARAM(itb, "Instruction TLB"),
550 INIT_PARAM(dtb, "Data TLB"),
551 INIT_PARAM(profile, ""),
552#else
553 INIT_PARAM(workload, "processes to run"),
554#endif // FULL_SYSTEM
555
556 INIT_PARAM(clock, "clock speed"),
557 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
558 INIT_PARAM(width, "cpu width"),
559 INIT_PARAM(function_trace, "Enable function trace"),
560 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
561 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
562
563END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
564
565
566CREATE_SIM_OBJECT(AtomicSimpleCPU)
567{
568 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
569 params->name = getInstanceName();
570 params->numberOfThreads = 1;
571 params->max_insts_any_thread = max_insts_any_thread;
572 params->max_insts_all_threads = max_insts_all_threads;
573 params->max_loads_any_thread = max_loads_any_thread;
574 params->max_loads_all_threads = max_loads_all_threads;
575 params->progress_interval = progress_interval;
576 params->deferRegistration = defer_registration;
577 params->clock = clock;
578 params->functionTrace = function_trace;
579 params->functionTraceStart = function_trace_start;
580 params->width = width;
581 params->simulate_stalls = simulate_stalls;
582 params->mem = mem;
583 params->system = system;
584 params->cpu_id = cpu_id;
585
586#if FULL_SYSTEM
587 params->itb = itb;
588 params->dtb = dtb;
589 params->profile = profile;
590#else
591 params->process = workload;
592#endif
593
594 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
595 return cpu;
596}
597
598REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
599
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