1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/atomic.hh"
35#include "mem/packet_impl.hh"
36#include "sim/builder.hh"
37#include "sim/system.hh"
38
39using namespace std;
40using namespace TheISA;
41
42AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
43 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
44{
45}
46
47
48void
49AtomicSimpleCPU::TickEvent::process()
50{
51 cpu->tick();
52}
53
54const char *
55AtomicSimpleCPU::TickEvent::description()
56{
57 return "AtomicSimpleCPU tick event";
58}
59
60Port *
61AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
62{
63 if (if_name == "dcache_port")
64 return &dcachePort;
65 else if (if_name == "icache_port")
66 return &icachePort;
67 else
68 panic("No Such Port\n");
69}
70
71void
72AtomicSimpleCPU::init()
73{
74 //Create Memory Ports (conect them up)
75// Port *mem_dport = mem->getPort("");
76// dcachePort.setPeer(mem_dport);
77// mem_dport->setPeer(&dcachePort);
78
79// Port *mem_iport = mem->getPort("");
80// icachePort.setPeer(mem_iport);
81// mem_iport->setPeer(&icachePort);
82
83 BaseCPU::init();
84#if FULL_SYSTEM
85 for (int i = 0; i < threadContexts.size(); ++i) {
86 ThreadContext *tc = threadContexts[i];
87
88 // initialize CPU, including PC
89 TheISA::initCPU(tc, tc->readCpuId());
90 }
91#endif
92}
93
94bool
95AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
96{
97 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
98 return true;
99}
100
101Tick
102AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
103{
104 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
105 return curTick;
106}
107
108void
109AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
110{
111 //No internal storage to update, just return
112 return;
113}
114
115void
116AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
117{
118 if (status == RangeChange)
119 return;
120
121 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
122}
123
124void
125AtomicSimpleCPU::CpuPort::recvRetry()
126{
127 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
128}
129
130
131AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
132 : BaseSimpleCPU(p), tickEvent(this),
133 width(p->width), simulate_stalls(p->simulate_stalls),
134 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
135{
136 _status = Idle;
137
138 ifetch_req = new Request();
139 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
140 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
141 ifetch_pkt->dataStatic(&inst);
142
143 data_read_req = new Request();
144 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
145 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
146 Packet::Broadcast);
147 data_read_pkt->dataStatic(&dataReg);
148
149 data_write_req = new Request();
150 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
151 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
152 Packet::Broadcast);
153}
154
155
156AtomicSimpleCPU::~AtomicSimpleCPU()
157{
158}
159
160void
161AtomicSimpleCPU::serialize(ostream &os)
162{
163 SimObject::State so_state = SimObject::getState();
164 SERIALIZE_ENUM(so_state);
165 Status _status = status();
166 SERIALIZE_ENUM(_status);
167 BaseSimpleCPU::serialize(os);
168 nameOut(os, csprintf("%s.tickEvent", name()));
169 tickEvent.serialize(os);
170}
171
172void
173AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
174{
175 SimObject::State so_state;
176 UNSERIALIZE_ENUM(so_state);
177 UNSERIALIZE_ENUM(_status);
178 BaseSimpleCPU::unserialize(cp, section);
179 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
180}
181
182void
183AtomicSimpleCPU::resume()
184{
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/atomic.hh"
35#include "mem/packet_impl.hh"
36#include "sim/builder.hh"
37#include "sim/system.hh"
38
39using namespace std;
40using namespace TheISA;
41
42AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
43 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
44{
45}
46
47
48void
49AtomicSimpleCPU::TickEvent::process()
50{
51 cpu->tick();
52}
53
54const char *
55AtomicSimpleCPU::TickEvent::description()
56{
57 return "AtomicSimpleCPU tick event";
58}
59
60Port *
61AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
62{
63 if (if_name == "dcache_port")
64 return &dcachePort;
65 else if (if_name == "icache_port")
66 return &icachePort;
67 else
68 panic("No Such Port\n");
69}
70
71void
72AtomicSimpleCPU::init()
73{
74 //Create Memory Ports (conect them up)
75// Port *mem_dport = mem->getPort("");
76// dcachePort.setPeer(mem_dport);
77// mem_dport->setPeer(&dcachePort);
78
79// Port *mem_iport = mem->getPort("");
80// icachePort.setPeer(mem_iport);
81// mem_iport->setPeer(&icachePort);
82
83 BaseCPU::init();
84#if FULL_SYSTEM
85 for (int i = 0; i < threadContexts.size(); ++i) {
86 ThreadContext *tc = threadContexts[i];
87
88 // initialize CPU, including PC
89 TheISA::initCPU(tc, tc->readCpuId());
90 }
91#endif
92}
93
94bool
95AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
96{
97 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
98 return true;
99}
100
101Tick
102AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
103{
104 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
105 return curTick;
106}
107
108void
109AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
110{
111 //No internal storage to update, just return
112 return;
113}
114
115void
116AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
117{
118 if (status == RangeChange)
119 return;
120
121 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
122}
123
124void
125AtomicSimpleCPU::CpuPort::recvRetry()
126{
127 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
128}
129
130
131AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
132 : BaseSimpleCPU(p), tickEvent(this),
133 width(p->width), simulate_stalls(p->simulate_stalls),
134 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
135{
136 _status = Idle;
137
138 ifetch_req = new Request();
139 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
140 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
141 ifetch_pkt->dataStatic(&inst);
142
143 data_read_req = new Request();
144 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
145 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
146 Packet::Broadcast);
147 data_read_pkt->dataStatic(&dataReg);
148
149 data_write_req = new Request();
150 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
151 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
152 Packet::Broadcast);
153}
154
155
156AtomicSimpleCPU::~AtomicSimpleCPU()
157{
158}
159
160void
161AtomicSimpleCPU::serialize(ostream &os)
162{
163 SimObject::State so_state = SimObject::getState();
164 SERIALIZE_ENUM(so_state);
165 Status _status = status();
166 SERIALIZE_ENUM(_status);
167 BaseSimpleCPU::serialize(os);
168 nameOut(os, csprintf("%s.tickEvent", name()));
169 tickEvent.serialize(os);
170}
171
172void
173AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
174{
175 SimObject::State so_state;
176 UNSERIALIZE_ENUM(so_state);
177 UNSERIALIZE_ENUM(_status);
178 BaseSimpleCPU::unserialize(cp, section);
179 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
180}
181
182void
183AtomicSimpleCPU::resume()
184{
|
188 if (!tickEvent.scheduled())
189 tickEvent.schedule(curTick);
190 }
191}
192
193void
194AtomicSimpleCPU::switchOut()
195{
196 assert(status() == Running || status() == Idle);
197 _status = SwitchedOut;
198
199 tickEvent.squash();
200}
201
202
203void
204AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
205{
206 BaseCPU::takeOverFrom(oldCPU);
207
208 assert(!tickEvent.scheduled());
209
210 // if any of this CPU's ThreadContexts are active, mark the CPU as
211 // running and schedule its tick event.
212 for (int i = 0; i < threadContexts.size(); ++i) {
213 ThreadContext *tc = threadContexts[i];
214 if (tc->status() == ThreadContext::Active && _status != Running) {
215 _status = Running;
216 tickEvent.schedule(curTick);
217 break;
218 }
219 }
220}
221
222
223void
224AtomicSimpleCPU::activateContext(int thread_num, int delay)
225{
226 assert(thread_num == 0);
227 assert(thread);
228
229 assert(_status == Idle);
230 assert(!tickEvent.scheduled());
231
232 notIdleFraction++;
233 tickEvent.schedule(curTick + cycles(delay));
234 _status = Running;
235}
236
237
238void
239AtomicSimpleCPU::suspendContext(int thread_num)
240{
241 assert(thread_num == 0);
242 assert(thread);
243
244 assert(_status == Running);
245
246 // tick event may not be scheduled if this gets called from inside
247 // an instruction's execution, e.g. "quiesce"
248 if (tickEvent.scheduled())
249 tickEvent.deschedule();
250
251 notIdleFraction--;
252 _status = Idle;
253}
254
255
256template <class T>
257Fault
258AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
259{
260 // use the CPU's statically allocated read request and packet objects
261 Request *req = data_read_req;
262 Packet *pkt = data_read_pkt;
263
264 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
265
266 if (traceData) {
267 traceData->setAddr(addr);
268 }
269
270 // translate to physical address
271 Fault fault = thread->translateDataReadReq(req);
272
273 // Now do the access.
274 if (fault == NoFault) {
275 pkt->reinitFromRequest();
276
277 dcache_latency = dcachePort.sendAtomic(pkt);
278 dcache_access = true;
279
280 assert(pkt->result == Packet::Success);
281 data = pkt->get<T>();
282
283 if (req->isLocked()) {
284 TheISA::handleLockedRead(thread, req);
285 }
286 }
287
288 // This will need a new way to tell if it has a dcache attached.
289 if (req->isUncacheable())
290 recordEvent("Uncached Read");
291
292 return fault;
293}
294
295#ifndef DOXYGEN_SHOULD_SKIP_THIS
296
297template
298Fault
299AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
300
301template
302Fault
303AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
304
305template
306Fault
307AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
308
309template
310Fault
311AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
312
313#endif //DOXYGEN_SHOULD_SKIP_THIS
314
315template<>
316Fault
317AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
318{
319 return read(addr, *(uint64_t*)&data, flags);
320}
321
322template<>
323Fault
324AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
325{
326 return read(addr, *(uint32_t*)&data, flags);
327}
328
329
330template<>
331Fault
332AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
333{
334 return read(addr, (uint32_t&)data, flags);
335}
336
337
338template <class T>
339Fault
340AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
341{
342 // use the CPU's statically allocated write request and packet objects
343 Request *req = data_write_req;
344 Packet *pkt = data_write_pkt;
345
346 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
347
348 if (traceData) {
349 traceData->setAddr(addr);
350 }
351
352 // translate to physical address
353 Fault fault = thread->translateDataWriteReq(req);
354
355 // Now do the access.
356 if (fault == NoFault) {
357 bool do_access = true; // flag to suppress cache access
358
359 if (req->isLocked()) {
360 do_access = TheISA::handleLockedWrite(thread, req);
361 }
362
363 if (do_access) {
364 data = htog(data);
365 pkt->reinitFromRequest();
366 pkt->dataStatic(&data);
367
368 dcache_latency = dcachePort.sendAtomic(pkt);
369 dcache_access = true;
370
371 assert(pkt->result == Packet::Success);
372 }
373
374 if (req->isLocked()) {
375 uint64_t scResult = req->getScResult();
376 if (scResult != 0) {
377 // clear failure counter
378 thread->setStCondFailures(0);
379 }
380 if (res) {
381 *res = req->getScResult();
382 }
383 }
384 }
385
386 // This will need a new way to tell if it's hooked up to a cache or not.
387 if (req->isUncacheable())
388 recordEvent("Uncached Write");
389
390 // If the write needs to have a fault on the access, consider calling
391 // changeStatus() and changing it to "bad addr write" or something.
392 return fault;
393}
394
395
396#ifndef DOXYGEN_SHOULD_SKIP_THIS
397template
398Fault
399AtomicSimpleCPU::write(uint64_t data, Addr addr,
400 unsigned flags, uint64_t *res);
401
402template
403Fault
404AtomicSimpleCPU::write(uint32_t data, Addr addr,
405 unsigned flags, uint64_t *res);
406
407template
408Fault
409AtomicSimpleCPU::write(uint16_t data, Addr addr,
410 unsigned flags, uint64_t *res);
411
412template
413Fault
414AtomicSimpleCPU::write(uint8_t data, Addr addr,
415 unsigned flags, uint64_t *res);
416
417#endif //DOXYGEN_SHOULD_SKIP_THIS
418
419template<>
420Fault
421AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
422{
423 return write(*(uint64_t*)&data, addr, flags, res);
424}
425
426template<>
427Fault
428AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
429{
430 return write(*(uint32_t*)&data, addr, flags, res);
431}
432
433
434template<>
435Fault
436AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
437{
438 return write((uint32_t)data, addr, flags, res);
439}
440
441
442void
443AtomicSimpleCPU::tick()
444{
445 Tick latency = cycles(1); // instruction takes one cycle by default
446
447 for (int i = 0; i < width; ++i) {
448 numCycles++;
449
450 checkForInterrupts();
451
452 Fault fault = setupFetchRequest(ifetch_req);
453
454 if (fault == NoFault) {
455 ifetch_pkt->reinitFromRequest();
456
457 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
458 // ifetch_req is initialized to read the instruction directly
459 // into the CPU object's inst field.
460
461 dcache_access = false; // assume no dcache access
462 preExecute();
463 fault = curStaticInst->execute(this, traceData);
464 postExecute();
465
466 if (simulate_stalls) {
467 Tick icache_stall = icache_latency - cycles(1);
468 Tick dcache_stall =
469 dcache_access ? dcache_latency - cycles(1) : 0;
470 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
471 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
472 latency += cycles(stall_cycles+1);
473 else
474 latency += cycles(stall_cycles);
475 }
476
477 }
478
479 advancePC(fault);
480 }
481
482 if (_status != Idle)
483 tickEvent.schedule(curTick + latency);
484}
485
486
487////////////////////////////////////////////////////////////////////////
488//
489// AtomicSimpleCPU Simulation Object
490//
491BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
492
493 Param<Counter> max_insts_any_thread;
494 Param<Counter> max_insts_all_threads;
495 Param<Counter> max_loads_any_thread;
496 Param<Counter> max_loads_all_threads;
497 Param<Tick> progress_interval;
498 SimObjectParam<MemObject *> mem;
499 SimObjectParam<System *> system;
500 Param<int> cpu_id;
501
502#if FULL_SYSTEM
503 SimObjectParam<AlphaITB *> itb;
504 SimObjectParam<AlphaDTB *> dtb;
505 Param<Tick> profile;
506#else
507 SimObjectParam<Process *> workload;
508#endif // FULL_SYSTEM
509
510 Param<int> clock;
511
512 Param<bool> defer_registration;
513 Param<int> width;
514 Param<bool> function_trace;
515 Param<Tick> function_trace_start;
516 Param<bool> simulate_stalls;
517
518END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
519
520BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
521
522 INIT_PARAM(max_insts_any_thread,
523 "terminate when any thread reaches this inst count"),
524 INIT_PARAM(max_insts_all_threads,
525 "terminate when all threads have reached this inst count"),
526 INIT_PARAM(max_loads_any_thread,
527 "terminate when any thread reaches this load count"),
528 INIT_PARAM(max_loads_all_threads,
529 "terminate when all threads have reached this load count"),
530 INIT_PARAM(progress_interval, "Progress interval"),
531 INIT_PARAM(mem, "memory"),
532 INIT_PARAM(system, "system object"),
533 INIT_PARAM(cpu_id, "processor ID"),
534
535#if FULL_SYSTEM
536 INIT_PARAM(itb, "Instruction TLB"),
537 INIT_PARAM(dtb, "Data TLB"),
538 INIT_PARAM(profile, ""),
539#else
540 INIT_PARAM(workload, "processes to run"),
541#endif // FULL_SYSTEM
542
543 INIT_PARAM(clock, "clock speed"),
544 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
545 INIT_PARAM(width, "cpu width"),
546 INIT_PARAM(function_trace, "Enable function trace"),
547 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
548 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
549
550END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
551
552
553CREATE_SIM_OBJECT(AtomicSimpleCPU)
554{
555 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
556 params->name = getInstanceName();
557 params->numberOfThreads = 1;
558 params->max_insts_any_thread = max_insts_any_thread;
559 params->max_insts_all_threads = max_insts_all_threads;
560 params->max_loads_any_thread = max_loads_any_thread;
561 params->max_loads_all_threads = max_loads_all_threads;
562 params->progress_interval = progress_interval;
563 params->deferRegistration = defer_registration;
564 params->clock = clock;
565 params->functionTrace = function_trace;
566 params->functionTraceStart = function_trace_start;
567 params->width = width;
568 params->simulate_stalls = simulate_stalls;
569 params->mem = mem;
570 params->system = system;
571 params->cpu_id = cpu_id;
572
573#if FULL_SYSTEM
574 params->itb = itb;
575 params->dtb = dtb;
576 params->profile = profile;
577#else
578 params->process = workload;
579#endif
580
581 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
582 return cpu;
583}
584
585REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
586
| 188 if (!tickEvent.scheduled())
189 tickEvent.schedule(curTick);
190 }
191}
192
193void
194AtomicSimpleCPU::switchOut()
195{
196 assert(status() == Running || status() == Idle);
197 _status = SwitchedOut;
198
199 tickEvent.squash();
200}
201
202
203void
204AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
205{
206 BaseCPU::takeOverFrom(oldCPU);
207
208 assert(!tickEvent.scheduled());
209
210 // if any of this CPU's ThreadContexts are active, mark the CPU as
211 // running and schedule its tick event.
212 for (int i = 0; i < threadContexts.size(); ++i) {
213 ThreadContext *tc = threadContexts[i];
214 if (tc->status() == ThreadContext::Active && _status != Running) {
215 _status = Running;
216 tickEvent.schedule(curTick);
217 break;
218 }
219 }
220}
221
222
223void
224AtomicSimpleCPU::activateContext(int thread_num, int delay)
225{
226 assert(thread_num == 0);
227 assert(thread);
228
229 assert(_status == Idle);
230 assert(!tickEvent.scheduled());
231
232 notIdleFraction++;
233 tickEvent.schedule(curTick + cycles(delay));
234 _status = Running;
235}
236
237
238void
239AtomicSimpleCPU::suspendContext(int thread_num)
240{
241 assert(thread_num == 0);
242 assert(thread);
243
244 assert(_status == Running);
245
246 // tick event may not be scheduled if this gets called from inside
247 // an instruction's execution, e.g. "quiesce"
248 if (tickEvent.scheduled())
249 tickEvent.deschedule();
250
251 notIdleFraction--;
252 _status = Idle;
253}
254
255
256template <class T>
257Fault
258AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
259{
260 // use the CPU's statically allocated read request and packet objects
261 Request *req = data_read_req;
262 Packet *pkt = data_read_pkt;
263
264 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
265
266 if (traceData) {
267 traceData->setAddr(addr);
268 }
269
270 // translate to physical address
271 Fault fault = thread->translateDataReadReq(req);
272
273 // Now do the access.
274 if (fault == NoFault) {
275 pkt->reinitFromRequest();
276
277 dcache_latency = dcachePort.sendAtomic(pkt);
278 dcache_access = true;
279
280 assert(pkt->result == Packet::Success);
281 data = pkt->get<T>();
282
283 if (req->isLocked()) {
284 TheISA::handleLockedRead(thread, req);
285 }
286 }
287
288 // This will need a new way to tell if it has a dcache attached.
289 if (req->isUncacheable())
290 recordEvent("Uncached Read");
291
292 return fault;
293}
294
295#ifndef DOXYGEN_SHOULD_SKIP_THIS
296
297template
298Fault
299AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
300
301template
302Fault
303AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
304
305template
306Fault
307AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
308
309template
310Fault
311AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
312
313#endif //DOXYGEN_SHOULD_SKIP_THIS
314
315template<>
316Fault
317AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
318{
319 return read(addr, *(uint64_t*)&data, flags);
320}
321
322template<>
323Fault
324AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
325{
326 return read(addr, *(uint32_t*)&data, flags);
327}
328
329
330template<>
331Fault
332AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
333{
334 return read(addr, (uint32_t&)data, flags);
335}
336
337
338template <class T>
339Fault
340AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
341{
342 // use the CPU's statically allocated write request and packet objects
343 Request *req = data_write_req;
344 Packet *pkt = data_write_pkt;
345
346 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
347
348 if (traceData) {
349 traceData->setAddr(addr);
350 }
351
352 // translate to physical address
353 Fault fault = thread->translateDataWriteReq(req);
354
355 // Now do the access.
356 if (fault == NoFault) {
357 bool do_access = true; // flag to suppress cache access
358
359 if (req->isLocked()) {
360 do_access = TheISA::handleLockedWrite(thread, req);
361 }
362
363 if (do_access) {
364 data = htog(data);
365 pkt->reinitFromRequest();
366 pkt->dataStatic(&data);
367
368 dcache_latency = dcachePort.sendAtomic(pkt);
369 dcache_access = true;
370
371 assert(pkt->result == Packet::Success);
372 }
373
374 if (req->isLocked()) {
375 uint64_t scResult = req->getScResult();
376 if (scResult != 0) {
377 // clear failure counter
378 thread->setStCondFailures(0);
379 }
380 if (res) {
381 *res = req->getScResult();
382 }
383 }
384 }
385
386 // This will need a new way to tell if it's hooked up to a cache or not.
387 if (req->isUncacheable())
388 recordEvent("Uncached Write");
389
390 // If the write needs to have a fault on the access, consider calling
391 // changeStatus() and changing it to "bad addr write" or something.
392 return fault;
393}
394
395
396#ifndef DOXYGEN_SHOULD_SKIP_THIS
397template
398Fault
399AtomicSimpleCPU::write(uint64_t data, Addr addr,
400 unsigned flags, uint64_t *res);
401
402template
403Fault
404AtomicSimpleCPU::write(uint32_t data, Addr addr,
405 unsigned flags, uint64_t *res);
406
407template
408Fault
409AtomicSimpleCPU::write(uint16_t data, Addr addr,
410 unsigned flags, uint64_t *res);
411
412template
413Fault
414AtomicSimpleCPU::write(uint8_t data, Addr addr,
415 unsigned flags, uint64_t *res);
416
417#endif //DOXYGEN_SHOULD_SKIP_THIS
418
419template<>
420Fault
421AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
422{
423 return write(*(uint64_t*)&data, addr, flags, res);
424}
425
426template<>
427Fault
428AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
429{
430 return write(*(uint32_t*)&data, addr, flags, res);
431}
432
433
434template<>
435Fault
436AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
437{
438 return write((uint32_t)data, addr, flags, res);
439}
440
441
442void
443AtomicSimpleCPU::tick()
444{
445 Tick latency = cycles(1); // instruction takes one cycle by default
446
447 for (int i = 0; i < width; ++i) {
448 numCycles++;
449
450 checkForInterrupts();
451
452 Fault fault = setupFetchRequest(ifetch_req);
453
454 if (fault == NoFault) {
455 ifetch_pkt->reinitFromRequest();
456
457 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
458 // ifetch_req is initialized to read the instruction directly
459 // into the CPU object's inst field.
460
461 dcache_access = false; // assume no dcache access
462 preExecute();
463 fault = curStaticInst->execute(this, traceData);
464 postExecute();
465
466 if (simulate_stalls) {
467 Tick icache_stall = icache_latency - cycles(1);
468 Tick dcache_stall =
469 dcache_access ? dcache_latency - cycles(1) : 0;
470 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
471 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
472 latency += cycles(stall_cycles+1);
473 else
474 latency += cycles(stall_cycles);
475 }
476
477 }
478
479 advancePC(fault);
480 }
481
482 if (_status != Idle)
483 tickEvent.schedule(curTick + latency);
484}
485
486
487////////////////////////////////////////////////////////////////////////
488//
489// AtomicSimpleCPU Simulation Object
490//
491BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
492
493 Param<Counter> max_insts_any_thread;
494 Param<Counter> max_insts_all_threads;
495 Param<Counter> max_loads_any_thread;
496 Param<Counter> max_loads_all_threads;
497 Param<Tick> progress_interval;
498 SimObjectParam<MemObject *> mem;
499 SimObjectParam<System *> system;
500 Param<int> cpu_id;
501
502#if FULL_SYSTEM
503 SimObjectParam<AlphaITB *> itb;
504 SimObjectParam<AlphaDTB *> dtb;
505 Param<Tick> profile;
506#else
507 SimObjectParam<Process *> workload;
508#endif // FULL_SYSTEM
509
510 Param<int> clock;
511
512 Param<bool> defer_registration;
513 Param<int> width;
514 Param<bool> function_trace;
515 Param<Tick> function_trace_start;
516 Param<bool> simulate_stalls;
517
518END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
519
520BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
521
522 INIT_PARAM(max_insts_any_thread,
523 "terminate when any thread reaches this inst count"),
524 INIT_PARAM(max_insts_all_threads,
525 "terminate when all threads have reached this inst count"),
526 INIT_PARAM(max_loads_any_thread,
527 "terminate when any thread reaches this load count"),
528 INIT_PARAM(max_loads_all_threads,
529 "terminate when all threads have reached this load count"),
530 INIT_PARAM(progress_interval, "Progress interval"),
531 INIT_PARAM(mem, "memory"),
532 INIT_PARAM(system, "system object"),
533 INIT_PARAM(cpu_id, "processor ID"),
534
535#if FULL_SYSTEM
536 INIT_PARAM(itb, "Instruction TLB"),
537 INIT_PARAM(dtb, "Data TLB"),
538 INIT_PARAM(profile, ""),
539#else
540 INIT_PARAM(workload, "processes to run"),
541#endif // FULL_SYSTEM
542
543 INIT_PARAM(clock, "clock speed"),
544 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
545 INIT_PARAM(width, "cpu width"),
546 INIT_PARAM(function_trace, "Enable function trace"),
547 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
548 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
549
550END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
551
552
553CREATE_SIM_OBJECT(AtomicSimpleCPU)
554{
555 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
556 params->name = getInstanceName();
557 params->numberOfThreads = 1;
558 params->max_insts_any_thread = max_insts_any_thread;
559 params->max_insts_all_threads = max_insts_all_threads;
560 params->max_loads_any_thread = max_loads_any_thread;
561 params->max_loads_all_threads = max_loads_all_threads;
562 params->progress_interval = progress_interval;
563 params->deferRegistration = defer_registration;
564 params->clock = clock;
565 params->functionTrace = function_trace;
566 params->functionTraceStart = function_trace_start;
567 params->width = width;
568 params->simulate_stalls = simulate_stalls;
569 params->mem = mem;
570 params->system = system;
571 params->cpu_id = cpu_id;
572
573#if FULL_SYSTEM
574 params->itb = itb;
575 params->dtb = dtb;
576 params->profile = profile;
577#else
578 params->process = workload;
579#endif
580
581 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
582 return cpu;
583}
584
585REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
586
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