1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/atomic.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36
37using namespace std;
38using namespace TheISA;
39
40AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
41 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
42{
43}
44
45
46void
47AtomicSimpleCPU::TickEvent::process()
48{
49 cpu->tick();
50}
51
52const char *
53AtomicSimpleCPU::TickEvent::description()
54{
55 return "AtomicSimpleCPU tick event";
56}
57
58
59void
60AtomicSimpleCPU::init()
61{
62 //Create Memory Ports (conect them up)
63 Port *mem_dport = mem->getPort("");
64 dcachePort.setPeer(mem_dport);
65 mem_dport->setPeer(&dcachePort);
66
67 Port *mem_iport = mem->getPort("");
68 icachePort.setPeer(mem_iport);
69 mem_iport->setPeer(&icachePort);
70
71 BaseCPU::init();
72#if FULL_SYSTEM
73 for (int i = 0; i < threadContexts.size(); ++i) {
74 ThreadContext *tc = threadContexts[i];
75
76 // initialize CPU, including PC
77 TheISA::initCPU(tc, tc->readCpuId());
78 }
79#endif
80}
81
82bool
83AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
84{
85 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
86 return true;
87}
88
89Tick
90AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
91{
92 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
93 return curTick;
94}
95
96void
97AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
98{
99 panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
100}
101
102void
103AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
104{
105 if (status == RangeChange)
106 return;
107
108 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
109}
110
111void
112AtomicSimpleCPU::CpuPort::recvRetry()
113{
114 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
115}
116
117
118AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
119 : BaseSimpleCPU(p), tickEvent(this),
120 width(p->width), simulate_stalls(p->simulate_stalls),
121 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
122{
123 _status = Idle;
124
125 // @todo fix me and get the real cpu id & thread number!!!
126 ifetch_req = new Request();
127 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
128 ifetch_pkt->dataStatic(&inst);
129
130 data_read_req = new Request();
131 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
132 Packet::Broadcast);
133 data_read_pkt->dataStatic(&dataReg);
134
135 data_write_req = new Request();
136 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
137 Packet::Broadcast);
138}
139
140
141AtomicSimpleCPU::~AtomicSimpleCPU()
142{
143}
144
145void
146AtomicSimpleCPU::serialize(ostream &os)
147{
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/atomic.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36
37using namespace std;
38using namespace TheISA;
39
40AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
41 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
42{
43}
44
45
46void
47AtomicSimpleCPU::TickEvent::process()
48{
49 cpu->tick();
50}
51
52const char *
53AtomicSimpleCPU::TickEvent::description()
54{
55 return "AtomicSimpleCPU tick event";
56}
57
58
59void
60AtomicSimpleCPU::init()
61{
62 //Create Memory Ports (conect them up)
63 Port *mem_dport = mem->getPort("");
64 dcachePort.setPeer(mem_dport);
65 mem_dport->setPeer(&dcachePort);
66
67 Port *mem_iport = mem->getPort("");
68 icachePort.setPeer(mem_iport);
69 mem_iport->setPeer(&icachePort);
70
71 BaseCPU::init();
72#if FULL_SYSTEM
73 for (int i = 0; i < threadContexts.size(); ++i) {
74 ThreadContext *tc = threadContexts[i];
75
76 // initialize CPU, including PC
77 TheISA::initCPU(tc, tc->readCpuId());
78 }
79#endif
80}
81
82bool
83AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
84{
85 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
86 return true;
87}
88
89Tick
90AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
91{
92 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
93 return curTick;
94}
95
96void
97AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
98{
99 panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
100}
101
102void
103AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
104{
105 if (status == RangeChange)
106 return;
107
108 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
109}
110
111void
112AtomicSimpleCPU::CpuPort::recvRetry()
113{
114 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
115}
116
117
118AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
119 : BaseSimpleCPU(p), tickEvent(this),
120 width(p->width), simulate_stalls(p->simulate_stalls),
121 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
122{
123 _status = Idle;
124
125 // @todo fix me and get the real cpu id & thread number!!!
126 ifetch_req = new Request();
127 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
128 ifetch_pkt->dataStatic(&inst);
129
130 data_read_req = new Request();
131 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
132 Packet::Broadcast);
133 data_read_pkt->dataStatic(&dataReg);
134
135 data_write_req = new Request();
136 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
137 Packet::Broadcast);
138}
139
140
141AtomicSimpleCPU::~AtomicSimpleCPU()
142{
143}
144
145void
146AtomicSimpleCPU::serialize(ostream &os)
147{
|
172}
173
174
175void
176AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
177{
178 BaseCPU::takeOverFrom(oldCPU);
179
180 assert(!tickEvent.scheduled());
181
182 // if any of this CPU's ThreadContexts are active, mark the CPU as
183 // running and schedule its tick event.
184 for (int i = 0; i < threadContexts.size(); ++i) {
185 ThreadContext *tc = threadContexts[i];
186 if (tc->status() == ThreadContext::Active && _status != Running) {
187 _status = Running;
188 tickEvent.schedule(curTick);
189 break;
190 }
191 }
192}
193
194
195void
196AtomicSimpleCPU::activateContext(int thread_num, int delay)
197{
198 assert(thread_num == 0);
199 assert(thread);
200
201 assert(_status == Idle);
202 assert(!tickEvent.scheduled());
203
204 notIdleFraction++;
205 tickEvent.schedule(curTick + cycles(delay));
206 _status = Running;
207}
208
209
210void
211AtomicSimpleCPU::suspendContext(int thread_num)
212{
213 assert(thread_num == 0);
214 assert(thread);
215
216 assert(_status == Running);
217
218 // tick event may not be scheduled if this gets called from inside
219 // an instruction's execution, e.g. "quiesce"
220 if (tickEvent.scheduled())
221 tickEvent.deschedule();
222
223 notIdleFraction--;
224 _status = Idle;
225}
226
227
228template <class T>
229Fault
230AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
231{
232 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
233
234 if (traceData) {
235 traceData->setAddr(addr);
236 }
237
238 // translate to physical address
239 Fault fault = thread->translateDataReadReq(data_read_req);
240
241 // Now do the access.
242 if (fault == NoFault) {
243 data_read_pkt->reinitFromRequest();
244
245 dcache_latency = dcachePort.sendAtomic(data_read_pkt);
246 dcache_access = true;
247
248 assert(data_read_pkt->result == Packet::Success);
249 data = data_read_pkt->get<T>();
250
251 }
252
253 // This will need a new way to tell if it has a dcache attached.
254 if (data_read_req->getFlags() & UNCACHEABLE)
255 recordEvent("Uncached Read");
256
257 return fault;
258}
259
260#ifndef DOXYGEN_SHOULD_SKIP_THIS
261
262template
263Fault
264AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
265
266template
267Fault
268AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
269
270template
271Fault
272AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
273
274template
275Fault
276AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
277
278#endif //DOXYGEN_SHOULD_SKIP_THIS
279
280template<>
281Fault
282AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
283{
284 return read(addr, *(uint64_t*)&data, flags);
285}
286
287template<>
288Fault
289AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
290{
291 return read(addr, *(uint32_t*)&data, flags);
292}
293
294
295template<>
296Fault
297AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
298{
299 return read(addr, (uint32_t&)data, flags);
300}
301
302
303template <class T>
304Fault
305AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
306{
307 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
308
309 if (traceData) {
310 traceData->setAddr(addr);
311 }
312
313 // translate to physical address
314 Fault fault = thread->translateDataWriteReq(data_write_req);
315
316 // Now do the access.
317 if (fault == NoFault) {
318 data = htog(data);
319 data_write_pkt->reinitFromRequest();
320 data_write_pkt->dataStatic(&data);
321
322 dcache_latency = dcachePort.sendAtomic(data_write_pkt);
323 dcache_access = true;
324
325 assert(data_write_pkt->result == Packet::Success);
326
327 if (res && data_write_req->getFlags() & LOCKED) {
328 *res = data_write_req->getScResult();
329 }
330 }
331
332 // This will need a new way to tell if it's hooked up to a cache or not.
333 if (data_write_req->getFlags() & UNCACHEABLE)
334 recordEvent("Uncached Write");
335
336 // If the write needs to have a fault on the access, consider calling
337 // changeStatus() and changing it to "bad addr write" or something.
338 return fault;
339}
340
341
342#ifndef DOXYGEN_SHOULD_SKIP_THIS
343template
344Fault
345AtomicSimpleCPU::write(uint64_t data, Addr addr,
346 unsigned flags, uint64_t *res);
347
348template
349Fault
350AtomicSimpleCPU::write(uint32_t data, Addr addr,
351 unsigned flags, uint64_t *res);
352
353template
354Fault
355AtomicSimpleCPU::write(uint16_t data, Addr addr,
356 unsigned flags, uint64_t *res);
357
358template
359Fault
360AtomicSimpleCPU::write(uint8_t data, Addr addr,
361 unsigned flags, uint64_t *res);
362
363#endif //DOXYGEN_SHOULD_SKIP_THIS
364
365template<>
366Fault
367AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
368{
369 return write(*(uint64_t*)&data, addr, flags, res);
370}
371
372template<>
373Fault
374AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
375{
376 return write(*(uint32_t*)&data, addr, flags, res);
377}
378
379
380template<>
381Fault
382AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
383{
384 return write((uint32_t)data, addr, flags, res);
385}
386
387
388void
389AtomicSimpleCPU::tick()
390{
391 Tick latency = cycles(1); // instruction takes one cycle by default
392
393 for (int i = 0; i < width; ++i) {
394 numCycles++;
395
396 checkForInterrupts();
397
398 Fault fault = setupFetchRequest(ifetch_req);
399
400 if (fault == NoFault) {
401 ifetch_pkt->reinitFromRequest();
402
403 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
404 // ifetch_req is initialized to read the instruction directly
405 // into the CPU object's inst field.
406
407 dcache_access = false; // assume no dcache access
408 preExecute();
409 fault = curStaticInst->execute(this, traceData);
410 postExecute();
411
412 if (simulate_stalls) {
413 // This calculation assumes that the icache and dcache
414 // access latencies are always a multiple of the CPU's
415 // cycle time. If not, the next tick event may get
416 // scheduled at a non-integer multiple of the CPU
417 // cycle time.
418 Tick icache_stall = icache_latency - cycles(1);
419 Tick dcache_stall =
420 dcache_access ? dcache_latency - cycles(1) : 0;
421 latency += icache_stall + dcache_stall;
422 }
423
424 }
425
426 advancePC(fault);
427 }
428
429 if (_status != Idle)
430 tickEvent.schedule(curTick + latency);
431}
432
433
434////////////////////////////////////////////////////////////////////////
435//
436// AtomicSimpleCPU Simulation Object
437//
438BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
439
440 Param<Counter> max_insts_any_thread;
441 Param<Counter> max_insts_all_threads;
442 Param<Counter> max_loads_any_thread;
443 Param<Counter> max_loads_all_threads;
444 SimObjectParam<MemObject *> mem;
445
446#if FULL_SYSTEM
447 SimObjectParam<AlphaITB *> itb;
448 SimObjectParam<AlphaDTB *> dtb;
449 SimObjectParam<System *> system;
450 Param<int> cpu_id;
451 Param<Tick> profile;
452#else
453 SimObjectParam<Process *> workload;
454#endif // FULL_SYSTEM
455
456 Param<int> clock;
457
458 Param<bool> defer_registration;
459 Param<int> width;
460 Param<bool> function_trace;
461 Param<Tick> function_trace_start;
462 Param<bool> simulate_stalls;
463
464END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
465
466BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
467
468 INIT_PARAM(max_insts_any_thread,
469 "terminate when any thread reaches this inst count"),
470 INIT_PARAM(max_insts_all_threads,
471 "terminate when all threads have reached this inst count"),
472 INIT_PARAM(max_loads_any_thread,
473 "terminate when any thread reaches this load count"),
474 INIT_PARAM(max_loads_all_threads,
475 "terminate when all threads have reached this load count"),
476 INIT_PARAM(mem, "memory"),
477
478#if FULL_SYSTEM
479 INIT_PARAM(itb, "Instruction TLB"),
480 INIT_PARAM(dtb, "Data TLB"),
481 INIT_PARAM(system, "system object"),
482 INIT_PARAM(cpu_id, "processor ID"),
483 INIT_PARAM(profile, ""),
484#else
485 INIT_PARAM(workload, "processes to run"),
486#endif // FULL_SYSTEM
487
488 INIT_PARAM(clock, "clock speed"),
489 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
490 INIT_PARAM(width, "cpu width"),
491 INIT_PARAM(function_trace, "Enable function trace"),
492 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
493 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
494
495END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
496
497
498CREATE_SIM_OBJECT(AtomicSimpleCPU)
499{
500 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
501 params->name = getInstanceName();
502 params->numberOfThreads = 1;
503 params->max_insts_any_thread = max_insts_any_thread;
504 params->max_insts_all_threads = max_insts_all_threads;
505 params->max_loads_any_thread = max_loads_any_thread;
506 params->max_loads_all_threads = max_loads_all_threads;
507 params->deferRegistration = defer_registration;
508 params->clock = clock;
509 params->functionTrace = function_trace;
510 params->functionTraceStart = function_trace_start;
511 params->width = width;
512 params->simulate_stalls = simulate_stalls;
513 params->mem = mem;
514
515#if FULL_SYSTEM
516 params->itb = itb;
517 params->dtb = dtb;
518 params->system = system;
519 params->cpu_id = cpu_id;
520 params->profile = profile;
521#else
522 params->process = workload;
523#endif
524
525 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
526 return cpu;
527}
528
529REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
530
| 169}
170
171
172void
173AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
174{
175 BaseCPU::takeOverFrom(oldCPU);
176
177 assert(!tickEvent.scheduled());
178
179 // if any of this CPU's ThreadContexts are active, mark the CPU as
180 // running and schedule its tick event.
181 for (int i = 0; i < threadContexts.size(); ++i) {
182 ThreadContext *tc = threadContexts[i];
183 if (tc->status() == ThreadContext::Active && _status != Running) {
184 _status = Running;
185 tickEvent.schedule(curTick);
186 break;
187 }
188 }
189}
190
191
192void
193AtomicSimpleCPU::activateContext(int thread_num, int delay)
194{
195 assert(thread_num == 0);
196 assert(thread);
197
198 assert(_status == Idle);
199 assert(!tickEvent.scheduled());
200
201 notIdleFraction++;
202 tickEvent.schedule(curTick + cycles(delay));
203 _status = Running;
204}
205
206
207void
208AtomicSimpleCPU::suspendContext(int thread_num)
209{
210 assert(thread_num == 0);
211 assert(thread);
212
213 assert(_status == Running);
214
215 // tick event may not be scheduled if this gets called from inside
216 // an instruction's execution, e.g. "quiesce"
217 if (tickEvent.scheduled())
218 tickEvent.deschedule();
219
220 notIdleFraction--;
221 _status = Idle;
222}
223
224
225template <class T>
226Fault
227AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
228{
229 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
230
231 if (traceData) {
232 traceData->setAddr(addr);
233 }
234
235 // translate to physical address
236 Fault fault = thread->translateDataReadReq(data_read_req);
237
238 // Now do the access.
239 if (fault == NoFault) {
240 data_read_pkt->reinitFromRequest();
241
242 dcache_latency = dcachePort.sendAtomic(data_read_pkt);
243 dcache_access = true;
244
245 assert(data_read_pkt->result == Packet::Success);
246 data = data_read_pkt->get<T>();
247
248 }
249
250 // This will need a new way to tell if it has a dcache attached.
251 if (data_read_req->getFlags() & UNCACHEABLE)
252 recordEvent("Uncached Read");
253
254 return fault;
255}
256
257#ifndef DOXYGEN_SHOULD_SKIP_THIS
258
259template
260Fault
261AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
262
263template
264Fault
265AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
266
267template
268Fault
269AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
270
271template
272Fault
273AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
274
275#endif //DOXYGEN_SHOULD_SKIP_THIS
276
277template<>
278Fault
279AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
280{
281 return read(addr, *(uint64_t*)&data, flags);
282}
283
284template<>
285Fault
286AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
287{
288 return read(addr, *(uint32_t*)&data, flags);
289}
290
291
292template<>
293Fault
294AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
295{
296 return read(addr, (uint32_t&)data, flags);
297}
298
299
300template <class T>
301Fault
302AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
303{
304 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
305
306 if (traceData) {
307 traceData->setAddr(addr);
308 }
309
310 // translate to physical address
311 Fault fault = thread->translateDataWriteReq(data_write_req);
312
313 // Now do the access.
314 if (fault == NoFault) {
315 data = htog(data);
316 data_write_pkt->reinitFromRequest();
317 data_write_pkt->dataStatic(&data);
318
319 dcache_latency = dcachePort.sendAtomic(data_write_pkt);
320 dcache_access = true;
321
322 assert(data_write_pkt->result == Packet::Success);
323
324 if (res && data_write_req->getFlags() & LOCKED) {
325 *res = data_write_req->getScResult();
326 }
327 }
328
329 // This will need a new way to tell if it's hooked up to a cache or not.
330 if (data_write_req->getFlags() & UNCACHEABLE)
331 recordEvent("Uncached Write");
332
333 // If the write needs to have a fault on the access, consider calling
334 // changeStatus() and changing it to "bad addr write" or something.
335 return fault;
336}
337
338
339#ifndef DOXYGEN_SHOULD_SKIP_THIS
340template
341Fault
342AtomicSimpleCPU::write(uint64_t data, Addr addr,
343 unsigned flags, uint64_t *res);
344
345template
346Fault
347AtomicSimpleCPU::write(uint32_t data, Addr addr,
348 unsigned flags, uint64_t *res);
349
350template
351Fault
352AtomicSimpleCPU::write(uint16_t data, Addr addr,
353 unsigned flags, uint64_t *res);
354
355template
356Fault
357AtomicSimpleCPU::write(uint8_t data, Addr addr,
358 unsigned flags, uint64_t *res);
359
360#endif //DOXYGEN_SHOULD_SKIP_THIS
361
362template<>
363Fault
364AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
365{
366 return write(*(uint64_t*)&data, addr, flags, res);
367}
368
369template<>
370Fault
371AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
372{
373 return write(*(uint32_t*)&data, addr, flags, res);
374}
375
376
377template<>
378Fault
379AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
380{
381 return write((uint32_t)data, addr, flags, res);
382}
383
384
385void
386AtomicSimpleCPU::tick()
387{
388 Tick latency = cycles(1); // instruction takes one cycle by default
389
390 for (int i = 0; i < width; ++i) {
391 numCycles++;
392
393 checkForInterrupts();
394
395 Fault fault = setupFetchRequest(ifetch_req);
396
397 if (fault == NoFault) {
398 ifetch_pkt->reinitFromRequest();
399
400 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
401 // ifetch_req is initialized to read the instruction directly
402 // into the CPU object's inst field.
403
404 dcache_access = false; // assume no dcache access
405 preExecute();
406 fault = curStaticInst->execute(this, traceData);
407 postExecute();
408
409 if (simulate_stalls) {
410 // This calculation assumes that the icache and dcache
411 // access latencies are always a multiple of the CPU's
412 // cycle time. If not, the next tick event may get
413 // scheduled at a non-integer multiple of the CPU
414 // cycle time.
415 Tick icache_stall = icache_latency - cycles(1);
416 Tick dcache_stall =
417 dcache_access ? dcache_latency - cycles(1) : 0;
418 latency += icache_stall + dcache_stall;
419 }
420
421 }
422
423 advancePC(fault);
424 }
425
426 if (_status != Idle)
427 tickEvent.schedule(curTick + latency);
428}
429
430
431////////////////////////////////////////////////////////////////////////
432//
433// AtomicSimpleCPU Simulation Object
434//
435BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
436
437 Param<Counter> max_insts_any_thread;
438 Param<Counter> max_insts_all_threads;
439 Param<Counter> max_loads_any_thread;
440 Param<Counter> max_loads_all_threads;
441 SimObjectParam<MemObject *> mem;
442
443#if FULL_SYSTEM
444 SimObjectParam<AlphaITB *> itb;
445 SimObjectParam<AlphaDTB *> dtb;
446 SimObjectParam<System *> system;
447 Param<int> cpu_id;
448 Param<Tick> profile;
449#else
450 SimObjectParam<Process *> workload;
451#endif // FULL_SYSTEM
452
453 Param<int> clock;
454
455 Param<bool> defer_registration;
456 Param<int> width;
457 Param<bool> function_trace;
458 Param<Tick> function_trace_start;
459 Param<bool> simulate_stalls;
460
461END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
462
463BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
464
465 INIT_PARAM(max_insts_any_thread,
466 "terminate when any thread reaches this inst count"),
467 INIT_PARAM(max_insts_all_threads,
468 "terminate when all threads have reached this inst count"),
469 INIT_PARAM(max_loads_any_thread,
470 "terminate when any thread reaches this load count"),
471 INIT_PARAM(max_loads_all_threads,
472 "terminate when all threads have reached this load count"),
473 INIT_PARAM(mem, "memory"),
474
475#if FULL_SYSTEM
476 INIT_PARAM(itb, "Instruction TLB"),
477 INIT_PARAM(dtb, "Data TLB"),
478 INIT_PARAM(system, "system object"),
479 INIT_PARAM(cpu_id, "processor ID"),
480 INIT_PARAM(profile, ""),
481#else
482 INIT_PARAM(workload, "processes to run"),
483#endif // FULL_SYSTEM
484
485 INIT_PARAM(clock, "clock speed"),
486 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
487 INIT_PARAM(width, "cpu width"),
488 INIT_PARAM(function_trace, "Enable function trace"),
489 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
490 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
491
492END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
493
494
495CREATE_SIM_OBJECT(AtomicSimpleCPU)
496{
497 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
498 params->name = getInstanceName();
499 params->numberOfThreads = 1;
500 params->max_insts_any_thread = max_insts_any_thread;
501 params->max_insts_all_threads = max_insts_all_threads;
502 params->max_loads_any_thread = max_loads_any_thread;
503 params->max_loads_all_threads = max_loads_all_threads;
504 params->deferRegistration = defer_registration;
505 params->clock = clock;
506 params->functionTrace = function_trace;
507 params->functionTraceStart = function_trace_start;
508 params->width = width;
509 params->simulate_stalls = simulate_stalls;
510 params->mem = mem;
511
512#if FULL_SYSTEM
513 params->itb = itb;
514 params->dtb = dtb;
515 params->system = system;
516 params->cpu_id = cpu_id;
517 params->profile = profile;
518#else
519 params->process = workload;
520#endif
521
522 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
523 return cpu;
524}
525
526REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
527
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