1/* 2 * Copyright 2014 Google, Inc.
| 1/* 2 * Copyright 2014 Google, Inc.
|
3 * Copyright (c) 2012-2013 ARM Limited
| 3 * Copyright (c) 2012-2013,2015 ARM Limited
|
4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/locked_mem.hh" 45#include "arch/mmapped_ipr.hh" 46#include "arch/utility.hh" 47#include "base/bigint.hh" 48#include "base/output.hh" 49#include "config/the_isa.hh" 50#include "cpu/simple/atomic.hh" 51#include "cpu/exetrace.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/SimpleCPU.hh" 55#include "mem/packet.hh" 56#include "mem/packet_access.hh" 57#include "mem/physical.hh" 58#include "params/AtomicSimpleCPU.hh" 59#include "sim/faults.hh" 60#include "sim/system.hh" 61#include "sim/full_system.hh" 62 63using namespace std; 64using namespace TheISA; 65 66AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 67 : Event(CPU_Tick_Pri), cpu(c) 68{ 69} 70 71 72void 73AtomicSimpleCPU::TickEvent::process() 74{ 75 cpu->tick(); 76} 77 78const char * 79AtomicSimpleCPU::TickEvent::description() const 80{ 81 return "AtomicSimpleCPU tick"; 82} 83 84void 85AtomicSimpleCPU::init() 86{
| 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2002-2005 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Steve Reinhardt 42 */ 43 44#include "arch/locked_mem.hh" 45#include "arch/mmapped_ipr.hh" 46#include "arch/utility.hh" 47#include "base/bigint.hh" 48#include "base/output.hh" 49#include "config/the_isa.hh" 50#include "cpu/simple/atomic.hh" 51#include "cpu/exetrace.hh" 52#include "debug/Drain.hh" 53#include "debug/ExecFaulting.hh" 54#include "debug/SimpleCPU.hh" 55#include "mem/packet.hh" 56#include "mem/packet_access.hh" 57#include "mem/physical.hh" 58#include "params/AtomicSimpleCPU.hh" 59#include "sim/faults.hh" 60#include "sim/system.hh" 61#include "sim/full_system.hh" 62 63using namespace std; 64using namespace TheISA; 65 66AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 67 : Event(CPU_Tick_Pri), cpu(c) 68{ 69} 70 71 72void 73AtomicSimpleCPU::TickEvent::process() 74{ 75 cpu->tick(); 76} 77 78const char * 79AtomicSimpleCPU::TickEvent::description() const 80{ 81 return "AtomicSimpleCPU tick"; 82} 83 84void 85AtomicSimpleCPU::init() 86{
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87 BaseCPU::init();
| 87 BaseSimpleCPU::init();
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88
| 88
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89 // Initialise the ThreadContext's memory proxies 90 tcBase()->initMemProxies(tcBase()); 91 92 if (FullSystem && !params()->switched_out) { 93 ThreadID size = threadContexts.size(); 94 for (ThreadID i = 0; i < size; ++i) { 95 ThreadContext *tc = threadContexts[i]; 96 // initialize CPU, including PC 97 TheISA::initCPU(tc, tc->contextId()); 98 } 99 } 100 101 // Atomic doesn't do MT right now, so contextId == threadId 102 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 103 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 104 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
| 89 ifetch_req.setThreadContext(_cpuId, 0); 90 data_read_req.setThreadContext(_cpuId, 0); 91 data_write_req.setThreadContext(_cpuId, 0);
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105} 106 107AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 108 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 109 simulate_data_stalls(p->simulate_data_stalls), 110 simulate_inst_stalls(p->simulate_inst_stalls), 111 icachePort(name() + ".icache_port", this), 112 dcachePort(name() + ".dcache_port", this), 113 fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 114 ppCommit(nullptr) 115{ 116 _status = Idle; 117} 118 119 120AtomicSimpleCPU::~AtomicSimpleCPU() 121{ 122 if (tickEvent.scheduled()) { 123 deschedule(tickEvent); 124 } 125} 126 127DrainState 128AtomicSimpleCPU::drain() 129{ 130 if (switchedOut()) 131 return DrainState::Drained; 132 133 if (!isDrained()) {
| 92} 93 94AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) 95 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), 96 simulate_data_stalls(p->simulate_data_stalls), 97 simulate_inst_stalls(p->simulate_inst_stalls), 98 icachePort(name() + ".icache_port", this), 99 dcachePort(name() + ".dcache_port", this), 100 fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 101 ppCommit(nullptr) 102{ 103 _status = Idle; 104} 105 106 107AtomicSimpleCPU::~AtomicSimpleCPU() 108{ 109 if (tickEvent.scheduled()) { 110 deschedule(tickEvent); 111 } 112} 113 114DrainState 115AtomicSimpleCPU::drain() 116{ 117 if (switchedOut()) 118 return DrainState::Drained; 119 120 if (!isDrained()) {
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134 DPRINTF(Drain, "Requesting drain: %s\n", pcState());
| 121 DPRINTF(Drain, "Requesting drain.\n");
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135 return DrainState::Draining; 136 } else { 137 if (tickEvent.scheduled()) 138 deschedule(tickEvent); 139
| 122 return DrainState::Draining; 123 } else { 124 if (tickEvent.scheduled()) 125 deschedule(tickEvent); 126
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| 127 activeThreads.clear();
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140 DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 141 return DrainState::Drained; 142 } 143} 144 145void 146AtomicSimpleCPU::drainResume() 147{ 148 assert(!tickEvent.scheduled()); 149 if (switchedOut()) 150 return; 151 152 DPRINTF(SimpleCPU, "Resume\n"); 153 verifyMemoryMode(); 154 155 assert(!threadContexts.empty());
| 128 DPRINTF(Drain, "Not executing microcode, no need to drain.\n"); 129 return DrainState::Drained; 130 } 131} 132 133void 134AtomicSimpleCPU::drainResume() 135{ 136 assert(!tickEvent.scheduled()); 137 if (switchedOut()) 138 return; 139 140 DPRINTF(SimpleCPU, "Resume\n"); 141 verifyMemoryMode(); 142 143 assert(!threadContexts.empty());
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156 if (threadContexts.size() > 1) 157 fatal("The atomic CPU only supports one thread.\n");
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158
| 144
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159 if (thread->status() == ThreadContext::Active) { 160 schedule(tickEvent, nextCycle()); 161 _status = BaseSimpleCPU::Running; 162 notIdleFraction = 1; 163 } else { 164 _status = BaseSimpleCPU::Idle; 165 notIdleFraction = 0;
| 145 _status = BaseSimpleCPU::Idle; 146 147 for (ThreadID tid = 0; tid < numThreads; tid++) { 148 if (threadInfo[tid]->thread->status() == ThreadContext::Active) { 149 threadInfo[tid]->notIdleFraction = 1; 150 activeThreads.push_back(tid); 151 _status = BaseSimpleCPU::Running; 152 153 // Tick if any threads active 154 if (!tickEvent.scheduled()) { 155 schedule(tickEvent, nextCycle()); 156 } 157 } else { 158 threadInfo[tid]->notIdleFraction = 0; 159 }
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166 } 167} 168 169bool 170AtomicSimpleCPU::tryCompleteDrain() 171{ 172 if (drainState() != DrainState::Draining) 173 return false; 174
| 160 } 161} 162 163bool 164AtomicSimpleCPU::tryCompleteDrain() 165{ 166 if (drainState() != DrainState::Draining) 167 return false; 168
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175 DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState());
| 169 DPRINTF(Drain, "tryCompleteDrain.\n");
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176 if (!isDrained()) 177 return false; 178 179 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 180 signalDrainDone(); 181 182 return true; 183} 184 185 186void 187AtomicSimpleCPU::switchOut() 188{ 189 BaseSimpleCPU::switchOut(); 190 191 assert(!tickEvent.scheduled()); 192 assert(_status == BaseSimpleCPU::Running || _status == Idle); 193 assert(isDrained()); 194} 195 196 197void 198AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 199{ 200 BaseSimpleCPU::takeOverFrom(oldCPU); 201 202 // The tick event should have been descheduled by drain() 203 assert(!tickEvent.scheduled());
| 170 if (!isDrained()) 171 return false; 172 173 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 174 signalDrainDone(); 175 176 return true; 177} 178 179 180void 181AtomicSimpleCPU::switchOut() 182{ 183 BaseSimpleCPU::switchOut(); 184 185 assert(!tickEvent.scheduled()); 186 assert(_status == BaseSimpleCPU::Running || _status == Idle); 187 assert(isDrained()); 188} 189 190 191void 192AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU) 193{ 194 BaseSimpleCPU::takeOverFrom(oldCPU); 195 196 // The tick event should have been descheduled by drain() 197 assert(!tickEvent.scheduled());
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204 205 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT 206 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too 207 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
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208} 209 210void 211AtomicSimpleCPU::verifyMemoryMode() const 212{ 213 if (!system->isAtomicMode()) { 214 fatal("The atomic CPU requires the memory system to be in " 215 "'atomic' mode.\n"); 216 } 217} 218 219void 220AtomicSimpleCPU::activateContext(ThreadID thread_num) 221{ 222 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 223
| 198} 199 200void 201AtomicSimpleCPU::verifyMemoryMode() const 202{ 203 if (!system->isAtomicMode()) { 204 fatal("The atomic CPU requires the memory system to be in " 205 "'atomic' mode.\n"); 206 } 207} 208 209void 210AtomicSimpleCPU::activateContext(ThreadID thread_num) 211{ 212 DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num); 213
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224 assert(thread_num == 0); 225 assert(thread);
| 214 assert(thread_num < numThreads);
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226
| 215
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227 assert(_status == Idle); 228 assert(!tickEvent.scheduled()); 229 230 notIdleFraction = 1; 231 Cycles delta = ticksToCycles(thread->lastActivate - thread->lastSuspend);
| 216 threadInfo[thread_num]->notIdleFraction = 1; 217 Cycles delta = ticksToCycles(threadInfo[thread_num]->thread->lastActivate - 218 threadInfo[thread_num]->thread->lastSuspend);
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232 numCycles += delta; 233 ppCycles->notify(delta); 234
| 219 numCycles += delta; 220 ppCycles->notify(delta); 221
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235 //Make sure ticks are still on multiples of cycles 236 schedule(tickEvent, clockEdge(Cycles(0)));
| 222 if (!tickEvent.scheduled()) { 223 //Make sure ticks are still on multiples of cycles 224 schedule(tickEvent, clockEdge(Cycles(0))); 225 }
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237 _status = BaseSimpleCPU::Running;
| 226 _status = BaseSimpleCPU::Running;
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| 227 if (std::find(activeThreads.begin(), activeThreads.end(), thread_num) 228 == activeThreads.end()) { 229 activeThreads.push_back(thread_num); 230 }
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238} 239 240 241void 242AtomicSimpleCPU::suspendContext(ThreadID thread_num) 243{ 244 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 245
| 231} 232 233 234void 235AtomicSimpleCPU::suspendContext(ThreadID thread_num) 236{ 237 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 238
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246 assert(thread_num == 0); 247 assert(thread);
| 239 assert(thread_num < numThreads); 240 activeThreads.remove(thread_num);
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248 249 if (_status == Idle) 250 return; 251 252 assert(_status == BaseSimpleCPU::Running); 253
| 241 242 if (_status == Idle) 243 return; 244 245 assert(_status == BaseSimpleCPU::Running); 246
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254 // tick event may not be scheduled if this gets called from inside 255 // an instruction's execution, e.g. "quiesce" 256 if (tickEvent.scheduled()) 257 deschedule(tickEvent);
| 247 threadInfo[thread_num]->notIdleFraction = 0;
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258
| 248
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259 notIdleFraction = 0; 260 _status = Idle;
| 249 if (activeThreads.empty()) { 250 _status = Idle; 251 252 if (tickEvent.scheduled()) { 253 deschedule(tickEvent); 254 } 255 } 256
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261} 262 263 264Tick 265AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 266{ 267 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 268 pkt->cmdString()); 269 270 // X86 ISA: Snooping an invalidation for monitor/mwait 271 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
| 257} 258 259 260Tick 261AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt) 262{ 263 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 264 pkt->cmdString()); 265 266 // X86 ISA: Snooping an invalidation for monitor/mwait 267 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
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272 if(cpu->getAddrMonitor()->doMonitor(pkt)) {
| 268 if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) {
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273 cpu->wakeup(); 274 } 275 276 // if snoop invalidates, release any associated locks 277 if (pkt->isInvalidate()) { 278 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 279 pkt->getAddr());
| 269 cpu->wakeup(); 270 } 271 272 // if snoop invalidates, release any associated locks 273 if (pkt->isInvalidate()) { 274 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 275 pkt->getAddr());
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280 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
| 276 for (auto &t_info : cpu->threadInfo) { 277 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 278 }
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281 } 282 283 return 0; 284} 285 286void 287AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 288{ 289 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 290 pkt->cmdString()); 291 292 // X86 ISA: Snooping an invalidation for monitor/mwait 293 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
| 279 } 280 281 return 0; 282} 283 284void 285AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt) 286{ 287 DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(), 288 pkt->cmdString()); 289 290 // X86 ISA: Snooping an invalidation for monitor/mwait 291 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)(&owner);
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294 if(cpu->getAddrMonitor()->doMonitor(pkt)) {
| 292 if(cpu->getCpuAddrMonitor()->doMonitor(pkt)) {
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295 cpu->wakeup(); 296 } 297 298 // if snoop invalidates, release any associated locks 299 if (pkt->isInvalidate()) { 300 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 301 pkt->getAddr());
| 293 cpu->wakeup(); 294 } 295 296 // if snoop invalidates, release any associated locks 297 if (pkt->isInvalidate()) { 298 DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n", 299 pkt->getAddr());
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302 TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
| 300 for (auto &t_info : cpu->threadInfo) { 301 TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask); 302 }
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303 } 304} 305 306Fault 307AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 308 unsigned size, unsigned flags) 309{
| 303 } 304} 305 306Fault 307AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, 308 unsigned size, unsigned flags) 309{
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| 310 SimpleExecContext& t_info = *threadInfo[curThread]; 311 SimpleThread* thread = t_info.thread; 312
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310 // use the CPU's statically allocated read request and packet objects 311 Request *req = &data_read_req; 312 313 if (traceData) 314 traceData->setMem(addr, size, flags); 315 316 //The size of the data we're trying to read. 317 int fullSize = size; 318 319 //The address of the second part of this access if it needs to be split 320 //across a cache line boundary. 321 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 322 323 if (secondAddr > addr) 324 size = secondAddr - addr; 325 326 dcache_latency = 0; 327 328 req->taskId(taskId()); 329 while (1) { 330 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 331 332 // translate to physical address
| 313 // use the CPU's statically allocated read request and packet objects 314 Request *req = &data_read_req; 315 316 if (traceData) 317 traceData->setMem(addr, size, flags); 318 319 //The size of the data we're trying to read. 320 int fullSize = size; 321 322 //The address of the second part of this access if it needs to be split 323 //across a cache line boundary. 324 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 325 326 if (secondAddr > addr) 327 size = secondAddr - addr; 328 329 dcache_latency = 0; 330 331 req->taskId(taskId()); 332 while (1) { 333 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 334 335 // translate to physical address
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333 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
| 336 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), 337 BaseTLB::Read);
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334 335 // Now do the access. 336 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 337 Packet pkt(req, Packet::makeReadCmd(req)); 338 pkt.dataStatic(data); 339 340 if (req->isMmappedIpr()) 341 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 342 else { 343 if (fastmem && system->isMemAddr(pkt.getAddr())) 344 system->getPhysMem().access(&pkt); 345 else 346 dcache_latency += dcachePort.sendAtomic(&pkt); 347 } 348 dcache_access = true; 349 350 assert(!pkt.isError()); 351 352 if (req->isLLSC()) { 353 TheISA::handleLockedRead(thread, req); 354 } 355 } 356 357 //If there's a fault, return it 358 if (fault != NoFault) { 359 if (req->isPrefetch()) { 360 return NoFault; 361 } else { 362 return fault; 363 } 364 } 365 366 //If we don't need to access a second cache line, stop now. 367 if (secondAddr <= addr) 368 { 369 if (req->isLockedRMW() && fault == NoFault) { 370 assert(!locked); 371 locked = true; 372 }
| 338 339 // Now do the access. 340 if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) { 341 Packet pkt(req, Packet::makeReadCmd(req)); 342 pkt.dataStatic(data); 343 344 if (req->isMmappedIpr()) 345 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt); 346 else { 347 if (fastmem && system->isMemAddr(pkt.getAddr())) 348 system->getPhysMem().access(&pkt); 349 else 350 dcache_latency += dcachePort.sendAtomic(&pkt); 351 } 352 dcache_access = true; 353 354 assert(!pkt.isError()); 355 356 if (req->isLLSC()) { 357 TheISA::handleLockedRead(thread, req); 358 } 359 } 360 361 //If there's a fault, return it 362 if (fault != NoFault) { 363 if (req->isPrefetch()) { 364 return NoFault; 365 } else { 366 return fault; 367 } 368 } 369 370 //If we don't need to access a second cache line, stop now. 371 if (secondAddr <= addr) 372 { 373 if (req->isLockedRMW() && fault == NoFault) { 374 assert(!locked); 375 locked = true; 376 }
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| 377
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373 return fault; 374 } 375 376 /* 377 * Set up for accessing the second cache line. 378 */ 379 380 //Move the pointer we're reading into to the correct location. 381 data += size; 382 //Adjust the size to get the remaining bytes. 383 size = addr + fullSize - secondAddr; 384 //And access the right address. 385 addr = secondAddr; 386 } 387} 388 389 390Fault 391AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 392 Addr addr, unsigned flags, uint64_t *res) 393{
| 378 return fault; 379 } 380 381 /* 382 * Set up for accessing the second cache line. 383 */ 384 385 //Move the pointer we're reading into to the correct location. 386 data += size; 387 //Adjust the size to get the remaining bytes. 388 size = addr + fullSize - secondAddr; 389 //And access the right address. 390 addr = secondAddr; 391 } 392} 393 394 395Fault 396AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, 397 Addr addr, unsigned flags, uint64_t *res) 398{
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394
| 399 SimpleExecContext& t_info = *threadInfo[curThread]; 400 SimpleThread* thread = t_info.thread;
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395 static uint8_t zero_array[64] = {}; 396 397 if (data == NULL) { 398 assert(size <= 64); 399 assert(flags & Request::CACHE_BLOCK_ZERO); 400 // This must be a cache block cleaning request 401 data = zero_array; 402 } 403 404 // use the CPU's statically allocated write request and packet objects 405 Request *req = &data_write_req; 406 407 if (traceData) 408 traceData->setMem(addr, size, flags); 409 410 //The size of the data we're trying to read. 411 int fullSize = size; 412 413 //The address of the second part of this access if it needs to be split 414 //across a cache line boundary. 415 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 416 417 if(secondAddr > addr) 418 size = secondAddr - addr; 419 420 dcache_latency = 0; 421 422 req->taskId(taskId()); 423 while(1) { 424 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 425 426 // translate to physical address
| 401 static uint8_t zero_array[64] = {}; 402 403 if (data == NULL) { 404 assert(size <= 64); 405 assert(flags & Request::CACHE_BLOCK_ZERO); 406 // This must be a cache block cleaning request 407 data = zero_array; 408 } 409 410 // use the CPU's statically allocated write request and packet objects 411 Request *req = &data_write_req; 412 413 if (traceData) 414 traceData->setMem(addr, size, flags); 415 416 //The size of the data we're trying to read. 417 int fullSize = size; 418 419 //The address of the second part of this access if it needs to be split 420 //across a cache line boundary. 421 Addr secondAddr = roundDown(addr + size - 1, cacheLineSize()); 422 423 if(secondAddr > addr) 424 size = secondAddr - addr; 425 426 dcache_latency = 0; 427 428 req->taskId(taskId()); 429 while(1) { 430 req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); 431 432 // translate to physical address
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427 Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
| 433 Fault fault = thread->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
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428 429 // Now do the access. 430 if (fault == NoFault) { 431 MemCmd cmd = MemCmd::WriteReq; // default 432 bool do_access = true; // flag to suppress cache access 433 434 if (req->isLLSC()) { 435 cmd = MemCmd::StoreCondReq; 436 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 437 } else if (req->isSwap()) { 438 cmd = MemCmd::SwapReq; 439 if (req->isCondSwap()) { 440 assert(res); 441 req->setExtraData(*res); 442 } 443 } 444 445 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 446 Packet pkt = Packet(req, cmd); 447 pkt.dataStatic(data); 448 449 if (req->isMmappedIpr()) { 450 dcache_latency += 451 TheISA::handleIprWrite(thread->getTC(), &pkt); 452 } else { 453 if (fastmem && system->isMemAddr(pkt.getAddr())) 454 system->getPhysMem().access(&pkt); 455 else 456 dcache_latency += dcachePort.sendAtomic(&pkt); 457 } 458 dcache_access = true; 459 assert(!pkt.isError()); 460 461 if (req->isSwap()) { 462 assert(res); 463 memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 464 } 465 } 466 467 if (res && !req->isSwap()) { 468 *res = req->getExtraData(); 469 } 470 } 471 472 //If there's a fault or we don't need to access a second cache line, 473 //stop now. 474 if (fault != NoFault || secondAddr <= addr) 475 { 476 if (req->isLockedRMW() && fault == NoFault) { 477 assert(locked); 478 locked = false; 479 }
| 434 435 // Now do the access. 436 if (fault == NoFault) { 437 MemCmd cmd = MemCmd::WriteReq; // default 438 bool do_access = true; // flag to suppress cache access 439 440 if (req->isLLSC()) { 441 cmd = MemCmd::StoreCondReq; 442 do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); 443 } else if (req->isSwap()) { 444 cmd = MemCmd::SwapReq; 445 if (req->isCondSwap()) { 446 assert(res); 447 req->setExtraData(*res); 448 } 449 } 450 451 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { 452 Packet pkt = Packet(req, cmd); 453 pkt.dataStatic(data); 454 455 if (req->isMmappedIpr()) { 456 dcache_latency += 457 TheISA::handleIprWrite(thread->getTC(), &pkt); 458 } else { 459 if (fastmem && system->isMemAddr(pkt.getAddr())) 460 system->getPhysMem().access(&pkt); 461 else 462 dcache_latency += dcachePort.sendAtomic(&pkt); 463 } 464 dcache_access = true; 465 assert(!pkt.isError()); 466 467 if (req->isSwap()) { 468 assert(res); 469 memcpy(res, pkt.getConstPtr<uint8_t>(), fullSize); 470 } 471 } 472 473 if (res && !req->isSwap()) { 474 *res = req->getExtraData(); 475 } 476 } 477 478 //If there's a fault or we don't need to access a second cache line, 479 //stop now. 480 if (fault != NoFault || secondAddr <= addr) 481 { 482 if (req->isLockedRMW() && fault == NoFault) { 483 assert(locked); 484 locked = false; 485 }
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| 486 487
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480 if (fault != NoFault && req->isPrefetch()) { 481 return NoFault; 482 } else { 483 return fault; 484 } 485 } 486 487 /* 488 * Set up for accessing the second cache line. 489 */ 490 491 //Move the pointer we're reading into to the correct location. 492 data += size; 493 //Adjust the size to get the remaining bytes. 494 size = addr + fullSize - secondAddr; 495 //And access the right address. 496 addr = secondAddr; 497 } 498} 499 500 501void 502AtomicSimpleCPU::tick() 503{ 504 DPRINTF(SimpleCPU, "Tick\n"); 505
| 488 if (fault != NoFault && req->isPrefetch()) { 489 return NoFault; 490 } else { 491 return fault; 492 } 493 } 494 495 /* 496 * Set up for accessing the second cache line. 497 */ 498 499 //Move the pointer we're reading into to the correct location. 500 data += size; 501 //Adjust the size to get the remaining bytes. 502 size = addr + fullSize - secondAddr; 503 //And access the right address. 504 addr = secondAddr; 505 } 506} 507 508 509void 510AtomicSimpleCPU::tick() 511{ 512 DPRINTF(SimpleCPU, "Tick\n"); 513
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| 514 // Change thread if multi-threaded 515 swapActiveThread(); 516 517 // Set memroy request ids to current thread 518 if (numThreads > 1) { 519 ifetch_req.setThreadContext(_cpuId, curThread); 520 data_read_req.setThreadContext(_cpuId, curThread); 521 data_write_req.setThreadContext(_cpuId, curThread); 522 } 523 524 SimpleExecContext& t_info = *threadInfo[curThread]; 525 SimpleThread* thread = t_info.thread; 526
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506 Tick latency = 0; 507 508 for (int i = 0; i < width || locked; ++i) { 509 numCycles++; 510 ppCycles->notify(1); 511 512 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 513 checkForInterrupts(); 514 checkPcEventQueue(); 515 } 516 517 // We must have just got suspended by a PC event 518 if (_status == Idle) { 519 tryCompleteDrain(); 520 return; 521 } 522 523 Fault fault = NoFault; 524 525 TheISA::PCState pcState = thread->pcState(); 526 527 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 528 !curMacroStaticInst; 529 if (needToFetch) { 530 ifetch_req.taskId(taskId()); 531 setupFetchRequest(&ifetch_req);
| 527 Tick latency = 0; 528 529 for (int i = 0; i < width || locked; ++i) { 530 numCycles++; 531 ppCycles->notify(1); 532 533 if (!curStaticInst || !curStaticInst->isDelayedCommit()) { 534 checkForInterrupts(); 535 checkPcEventQueue(); 536 } 537 538 // We must have just got suspended by a PC event 539 if (_status == Idle) { 540 tryCompleteDrain(); 541 return; 542 } 543 544 Fault fault = NoFault; 545 546 TheISA::PCState pcState = thread->pcState(); 547 548 bool needToFetch = !isRomMicroPC(pcState.microPC()) && 549 !curMacroStaticInst; 550 if (needToFetch) { 551 ifetch_req.taskId(taskId()); 552 setupFetchRequest(&ifetch_req);
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532 fault = thread->itb->translateAtomic(&ifetch_req, tc,
| 553 fault = thread->itb->translateAtomic(&ifetch_req, thread->getTC(),
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533 BaseTLB::Execute); 534 } 535 536 if (fault == NoFault) { 537 Tick icache_latency = 0; 538 bool icache_access = false; 539 dcache_access = false; // assume no dcache access 540 541 if (needToFetch) { 542 // This is commented out because the decoder would act like 543 // a tiny cache otherwise. It wouldn't be flushed when needed 544 // like the I cache. It should be flushed, and when that works 545 // this code should be uncommented. 546 //Fetch more instruction memory if necessary 547 //if(decoder.needMoreBytes()) 548 //{ 549 icache_access = true; 550 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 551 ifetch_pkt.dataStatic(&inst); 552 553 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 554 system->getPhysMem().access(&ifetch_pkt); 555 else 556 icache_latency = icachePort.sendAtomic(&ifetch_pkt); 557 558 assert(!ifetch_pkt.isError()); 559 560 // ifetch_req is initialized to read the instruction directly 561 // into the CPU object's inst field. 562 //} 563 } 564 565 preExecute(); 566 567 if (curStaticInst) {
| 554 BaseTLB::Execute); 555 } 556 557 if (fault == NoFault) { 558 Tick icache_latency = 0; 559 bool icache_access = false; 560 dcache_access = false; // assume no dcache access 561 562 if (needToFetch) { 563 // This is commented out because the decoder would act like 564 // a tiny cache otherwise. It wouldn't be flushed when needed 565 // like the I cache. It should be flushed, and when that works 566 // this code should be uncommented. 567 //Fetch more instruction memory if necessary 568 //if(decoder.needMoreBytes()) 569 //{ 570 icache_access = true; 571 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq); 572 ifetch_pkt.dataStatic(&inst); 573 574 if (fastmem && system->isMemAddr(ifetch_pkt.getAddr())) 575 system->getPhysMem().access(&ifetch_pkt); 576 else 577 icache_latency = icachePort.sendAtomic(&ifetch_pkt); 578 579 assert(!ifetch_pkt.isError()); 580 581 // ifetch_req is initialized to read the instruction directly 582 // into the CPU object's inst field. 583 //} 584 } 585 586 preExecute(); 587 588 if (curStaticInst) {
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568 fault = curStaticInst->execute(this, traceData);
| 589 fault = curStaticInst->execute(&t_info, traceData);
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569 570 // keep an instruction count 571 if (fault == NoFault) { 572 countInst(); 573 ppCommit->notify(std::make_pair(thread, curStaticInst)); 574 } 575 else if (traceData && !DTRACE(ExecFaulting)) { 576 delete traceData; 577 traceData = NULL; 578 } 579 580 postExecute(); 581 } 582 583 // @todo remove me after debugging with legion done 584 if (curStaticInst && (!curStaticInst->isMicroop() || 585 curStaticInst->isFirstMicroop())) 586 instCnt++; 587 588 Tick stall_ticks = 0; 589 if (simulate_inst_stalls && icache_access) 590 stall_ticks += icache_latency; 591 592 if (simulate_data_stalls && dcache_access) 593 stall_ticks += dcache_latency; 594 595 if (stall_ticks) { 596 // the atomic cpu does its accounting in ticks, so 597 // keep counting in ticks but round to the clock 598 // period 599 latency += divCeil(stall_ticks, clockPeriod()) * 600 clockPeriod(); 601 } 602 603 }
| 590 591 // keep an instruction count 592 if (fault == NoFault) { 593 countInst(); 594 ppCommit->notify(std::make_pair(thread, curStaticInst)); 595 } 596 else if (traceData && !DTRACE(ExecFaulting)) { 597 delete traceData; 598 traceData = NULL; 599 } 600 601 postExecute(); 602 } 603 604 // @todo remove me after debugging with legion done 605 if (curStaticInst && (!curStaticInst->isMicroop() || 606 curStaticInst->isFirstMicroop())) 607 instCnt++; 608 609 Tick stall_ticks = 0; 610 if (simulate_inst_stalls && icache_access) 611 stall_ticks += icache_latency; 612 613 if (simulate_data_stalls && dcache_access) 614 stall_ticks += dcache_latency; 615 616 if (stall_ticks) { 617 // the atomic cpu does its accounting in ticks, so 618 // keep counting in ticks but round to the clock 619 // period 620 latency += divCeil(stall_ticks, clockPeriod()) * 621 clockPeriod(); 622 } 623 624 }
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604 if(fault != NoFault || !stayAtPC)
| 625 if(fault != NoFault || !t_info.stayAtPC)
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605 advancePC(fault); 606 } 607 608 if (tryCompleteDrain()) 609 return; 610 611 // instruction takes at least one cycle 612 if (latency < clockPeriod()) 613 latency = clockPeriod(); 614 615 if (_status != Idle)
| 626 advancePC(fault); 627 } 628 629 if (tryCompleteDrain()) 630 return; 631 632 // instruction takes at least one cycle 633 if (latency < clockPeriod()) 634 latency = clockPeriod(); 635 636 if (_status != Idle)
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616 schedule(tickEvent, curTick() + latency);
| 637 reschedule(tickEvent, curTick() + latency, true);
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617} 618 619void 620AtomicSimpleCPU::regProbePoints() 621{ 622 BaseCPU::regProbePoints(); 623 624 ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 625 (getProbeManager(), "Commit"); 626} 627 628void 629AtomicSimpleCPU::printAddr(Addr a) 630{ 631 dcachePort.printAddr(a); 632} 633 634//////////////////////////////////////////////////////////////////////// 635// 636// AtomicSimpleCPU Simulation Object 637// 638AtomicSimpleCPU * 639AtomicSimpleCPUParams::create() 640{
| 638} 639 640void 641AtomicSimpleCPU::regProbePoints() 642{ 643 BaseCPU::regProbePoints(); 644 645 ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>> 646 (getProbeManager(), "Commit"); 647} 648 649void 650AtomicSimpleCPU::printAddr(Addr a) 651{ 652 dcachePort.printAddr(a); 653} 654 655//////////////////////////////////////////////////////////////////////// 656// 657// AtomicSimpleCPU Simulation Object 658// 659AtomicSimpleCPU * 660AtomicSimpleCPUParams::create() 661{
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641 numThreads = 1; 642 if (!FullSystem && workload.size() != 1) 643 panic("only one workload allowed");
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644 return new AtomicSimpleCPU(this); 645}
| 662 return new AtomicSimpleCPU(this); 663}
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