atomic.cc (8832:247fee427324) | atomic.cc (8850:ed91b534ed04) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 54 unchanged lines hidden (view full) --- 63AtomicSimpleCPU::TickEvent::description() const 64{ 65 return "AtomicSimpleCPU tick"; 66} 67 68Port * 69AtomicSimpleCPU::getPort(const string &if_name, int idx) 70{ | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 54 unchanged lines hidden (view full) --- 63AtomicSimpleCPU::TickEvent::description() const 64{ 65 return "AtomicSimpleCPU tick"; 66} 67 68Port * 69AtomicSimpleCPU::getPort(const string &if_name, int idx) 70{ |
71 if (if_name == "dcache_port") 72 return &dcachePort; 73 else if (if_name == "icache_port") 74 return &icachePort; 75 else if (if_name == "physmem_port") { | 71 if (if_name == "physmem_port") { |
76 hasPhysMemPort = true; 77 return &physmemPort; | 72 hasPhysMemPort = true; 73 return &physmemPort; |
74 } else { 75 return BaseCPU::getPort(if_name, idx); |
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78 } | 76 } |
79 else 80 panic("No Such Port\n"); | |
81} 82 83void 84AtomicSimpleCPU::init() 85{ 86 BaseCPU::init(); 87 if (FullSystem) { 88 ThreadID size = threadContexts.size(); --- 479 unchanged lines hidden --- | 77} 78 79void 80AtomicSimpleCPU::init() 81{ 82 BaseCPU::init(); 83 if (FullSystem) { 84 ThreadID size = threadContexts.size(); --- 479 unchanged lines hidden --- |