atomic.cc (4928:951bd17db218) | atomic.cc (4940:23874ae87540) |
---|---|
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 169 unchanged lines hidden (view full) --- 178 UNSERIALIZE_ENUM(_status); 179 BaseSimpleCPU::unserialize(cp, section); 180 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 181} 182 183void 184AtomicSimpleCPU::resume() 185{ | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 169 unchanged lines hidden (view full) --- 178 UNSERIALIZE_ENUM(_status); 179 BaseSimpleCPU::unserialize(cp, section); 180 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); 181} 182 183void 184AtomicSimpleCPU::resume() 185{ |
186 DPRINTF(SimpleCPU, "Resume\n"); |
|
186 if (_status != SwitchedOut && _status != Idle) { 187 assert(system->getMemoryMode() == Enums::atomic); 188 189 changeState(SimObject::Running); 190 if (thread->status() == ThreadContext::Active) { 191 if (!tickEvent.scheduled()) { 192 tickEvent.schedule(nextCycle()); 193 } --- 32 unchanged lines hidden (view full) --- 226 _status = Idle; 227 } 228} 229 230 231void 232AtomicSimpleCPU::activateContext(int thread_num, int delay) 233{ | 187 if (_status != SwitchedOut && _status != Idle) { 188 assert(system->getMemoryMode() == Enums::atomic); 189 190 changeState(SimObject::Running); 191 if (thread->status() == ThreadContext::Active) { 192 if (!tickEvent.scheduled()) { 193 tickEvent.schedule(nextCycle()); 194 } --- 32 unchanged lines hidden (view full) --- 227 _status = Idle; 228 } 229} 230 231 232void 233AtomicSimpleCPU::activateContext(int thread_num, int delay) 234{ |
235 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 236 |
|
234 assert(thread_num == 0); 235 assert(thread); 236 237 assert(_status == Idle); 238 assert(!tickEvent.scheduled()); 239 240 notIdleFraction++; 241 242 //Make sure ticks are still on multiples of cycles 243 tickEvent.schedule(nextCycle(curTick + cycles(delay))); 244 _status = Running; 245} 246 247 248void 249AtomicSimpleCPU::suspendContext(int thread_num) 250{ | 237 assert(thread_num == 0); 238 assert(thread); 239 240 assert(_status == Idle); 241 assert(!tickEvent.scheduled()); 242 243 notIdleFraction++; 244 245 //Make sure ticks are still on multiples of cycles 246 tickEvent.schedule(nextCycle(curTick + cycles(delay))); 247 _status = Running; 248} 249 250 251void 252AtomicSimpleCPU::suspendContext(int thread_num) 253{ |
254 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 255 |
|
251 assert(thread_num == 0); 252 assert(thread); 253 254 assert(_status == Running); 255 256 // tick event may not be scheduled if this gets called from inside 257 // an instruction's execution, e.g. "quiesce" 258 if (tickEvent.scheduled()) --- 219 unchanged lines hidden (view full) --- 478{ 479 return write((uint32_t)data, addr, flags, res); 480} 481 482 483void 484AtomicSimpleCPU::tick() 485{ | 256 assert(thread_num == 0); 257 assert(thread); 258 259 assert(_status == Running); 260 261 // tick event may not be scheduled if this gets called from inside 262 // an instruction's execution, e.g. "quiesce" 263 if (tickEvent.scheduled()) --- 219 unchanged lines hidden (view full) --- 483{ 484 return write((uint32_t)data, addr, flags, res); 485} 486 487 488void 489AtomicSimpleCPU::tick() 490{ |
491 DPRINTF(SimpleCPU, "Tick\n"); 492 |
|
486 Tick latency = cycles(1); // instruction takes one cycle by default 487 488 for (int i = 0; i < width; ++i) { 489 numCycles++; 490 491 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 492 checkForInterrupts(); 493 --- 97 unchanged lines hidden --- | 493 Tick latency = cycles(1); // instruction takes one cycle by default 494 495 for (int i = 0; i < width; ++i) { 496 numCycles++; 497 498 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 499 checkForInterrupts(); 500 --- 97 unchanged lines hidden --- |