atomic.cc (4027:53292b42ee1c) | atomic.cc (4040:eb894f3fc168) |
---|---|
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" 32#include "arch/mmaped_ipr.hh" 33#include "arch/utility.hh" | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 17 unchanged lines hidden (view full) --- 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" 32#include "arch/mmaped_ipr.hh" 33#include "arch/utility.hh" |
34#include "base/bigint.hh" |
|
34#include "cpu/exetrace.hh" 35#include "cpu/simple/atomic.hh" 36#include "mem/packet.hh" 37#include "mem/packet_access.hh" 38#include "sim/builder.hh" 39#include "sim/system.hh" 40 41using namespace std; --- 104 unchanged lines hidden (view full) --- 146 data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq, 147 Packet::Broadcast); 148 data_read_pkt->dataStatic(&dataReg); 149 150 data_write_req = new Request(); 151 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 152 data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq, 153 Packet::Broadcast); | 35#include "cpu/exetrace.hh" 36#include "cpu/simple/atomic.hh" 37#include "mem/packet.hh" 38#include "mem/packet_access.hh" 39#include "sim/builder.hh" 40#include "sim/system.hh" 41 42using namespace std; --- 104 unchanged lines hidden (view full) --- 147 data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq, 148 Packet::Broadcast); 149 data_read_pkt->dataStatic(&dataReg); 150 151 data_write_req = new Request(); 152 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too 153 data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq, 154 Packet::Broadcast); |
155 data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq, 156 Packet::Broadcast); |
|
154} 155 156 157AtomicSimpleCPU::~AtomicSimpleCPU() 158{ 159} 160 161void --- 151 unchanged lines hidden (view full) --- 313 314 return fault; 315} 316 317#ifndef DOXYGEN_SHOULD_SKIP_THIS 318 319template 320Fault | 157} 158 159 160AtomicSimpleCPU::~AtomicSimpleCPU() 161{ 162} 163 164void --- 151 unchanged lines hidden (view full) --- 316 317 return fault; 318} 319 320#ifndef DOXYGEN_SHOULD_SKIP_THIS 321 322template 323Fault |
324AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags); 325 326template 327Fault |
|
321AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 322 323template 324Fault 325AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 326 327template 328Fault --- 29 unchanged lines hidden (view full) --- 358 359 360template <class T> 361Fault 362AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 363{ 364 // use the CPU's statically allocated write request and packet objects 365 Request *req = data_write_req; | 328AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags); 329 330template 331Fault 332AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags); 333 334template 335Fault --- 29 unchanged lines hidden (view full) --- 365 366 367template <class T> 368Fault 369AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 370{ 371 // use the CPU's statically allocated write request and packet objects 372 Request *req = data_write_req; |
366 PacketPtr pkt = data_write_pkt; | 373 PacketPtr pkt; |
367 368 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 369 | 374 375 req->setVirt(0, addr, sizeof(T), flags, thread->readPC()); 376 |
377 if (req->isSwap()) 378 pkt = data_swap_pkt; 379 else 380 pkt = data_write_pkt; 381 |
|
370 if (traceData) { 371 traceData->setAddr(addr); 372 } 373 374 // translate to physical address 375 Fault fault = thread->translateDataWriteReq(req); 376 377 // Now do the access. 378 if (fault == NoFault) { 379 bool do_access = true; // flag to suppress cache access 380 381 if (req->isLocked()) { 382 do_access = TheISA::handleLockedWrite(thread, req); 383 } | 382 if (traceData) { 383 traceData->setAddr(addr); 384 } 385 386 // translate to physical address 387 Fault fault = thread->translateDataWriteReq(req); 388 389 // Now do the access. 390 if (fault == NoFault) { 391 bool do_access = true; // flag to suppress cache access 392 393 if (req->isLocked()) { 394 do_access = TheISA::handleLockedWrite(thread, req); 395 } |
396 if (req->isCondSwap()) { 397 assert(res); 398 req->setExtraData(*res); 399 } |
|
384 | 400 |
401 |
|
385 if (do_access) { 386 pkt->reinitFromRequest(); 387 pkt->dataStatic(&data); 388 389 if (req->isMmapedIpr()) { 390 dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt); 391 } else { 392 data = htog(data); 393 dcache_latency = dcachePort.sendAtomic(pkt); 394 } 395 dcache_access = true; 396 397#if !defined(NDEBUG) 398 if (pkt->result != Packet::Success) 399 panic("Unable to find responder for address pa = %#X va = %#X\n", 400 pkt->req->getPaddr(), pkt->req->getVaddr()); 401#endif 402 } 403 | 402 if (do_access) { 403 pkt->reinitFromRequest(); 404 pkt->dataStatic(&data); 405 406 if (req->isMmapedIpr()) { 407 dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt); 408 } else { 409 data = htog(data); 410 dcache_latency = dcachePort.sendAtomic(pkt); 411 } 412 dcache_access = true; 413 414#if !defined(NDEBUG) 415 if (pkt->result != Packet::Success) 416 panic("Unable to find responder for address pa = %#X va = %#X\n", 417 pkt->req->getPaddr(), pkt->req->getVaddr()); 418#endif 419 } 420 |
404 if (res) { 405 *res = req->getScResult(); | 421 if (req->isSwap()) { 422 assert(res); 423 *res = pkt->get<T>(); |
406 } | 424 } |
425 426 if (req->isLocked()) { 427 uint64_t scResult = req->getExtraData(); 428 if (scResult != 0) { 429 // clear failure counter 430 thread->setStCondFailures(0); 431 } 432 if (res) { 433 *res = req->getExtraData(); 434 } 435 } |
|
407 } 408 409 // This will need a new way to tell if it's hooked up to a cache or not. 410 if (req->isUncacheable()) 411 recordEvent("Uncached Write"); 412 413 // If the write needs to have a fault on the access, consider calling 414 // changeStatus() and changing it to "bad addr write" or something. --- 212 unchanged lines hidden --- | 436 } 437 438 // This will need a new way to tell if it's hooked up to a cache or not. 439 if (req->isUncacheable()) 440 recordEvent("Uncached Write"); 441 442 // If the write needs to have a fault on the access, consider calling 443 // changeStatus() and changing it to "bad addr write" or something. --- 212 unchanged lines hidden --- |