atomic.cc (3686:fa8d8b90cd8a) | atomic.cc (3806:65ae5388c059) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 15 unchanged lines hidden (view full) --- 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/locked_mem.hh" |
32#include "arch/mmaped_ipr.hh" |
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32#include "arch/utility.hh" 33#include "cpu/exetrace.hh" 34#include "cpu/simple/atomic.hh" 35#include "mem/packet.hh" 36#include "mem/packet_access.hh" 37#include "sim/builder.hh" 38#include "sim/system.hh" 39 --- 32 unchanged lines hidden (view full) --- 72void 73AtomicSimpleCPU::init() 74{ 75 BaseCPU::init(); 76#if FULL_SYSTEM 77 for (int i = 0; i < threadContexts.size(); ++i) { 78 ThreadContext *tc = threadContexts[i]; 79 | 33#include "arch/utility.hh" 34#include "cpu/exetrace.hh" 35#include "cpu/simple/atomic.hh" 36#include "mem/packet.hh" 37#include "mem/packet_access.hh" 38#include "sim/builder.hh" 39#include "sim/system.hh" 40 --- 32 unchanged lines hidden (view full) --- 73void 74AtomicSimpleCPU::init() 75{ 76 BaseCPU::init(); 77#if FULL_SYSTEM 78 for (int i = 0; i < threadContexts.size(); ++i) { 79 ThreadContext *tc = threadContexts[i]; 80 |
81 // initialize the mem pointers 82 tc->init(); 83 |
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80 // initialize CPU, including PC 81 TheISA::initCPU(tc, tc->readCpuId()); 82 } 83#endif 84} 85 86bool 87AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) --- 144 unchanged lines hidden (view full) --- 232{ 233 assert(thread_num == 0); 234 assert(thread); 235 236 assert(_status == Idle); 237 assert(!tickEvent.scheduled()); 238 239 notIdleFraction++; | 84 // initialize CPU, including PC 85 TheISA::initCPU(tc, tc->readCpuId()); 86 } 87#endif 88} 89 90bool 91AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt) --- 144 unchanged lines hidden (view full) --- 236{ 237 assert(thread_num == 0); 238 assert(thread); 239 240 assert(_status == Idle); 241 assert(!tickEvent.scheduled()); 242 243 notIdleFraction++; |
240 241#if FULL_SYSTEM 242 // Connect the ThreadContext's memory ports (Functional/Virtual 243 // Ports) 244 tc->connectMemPorts(); 245#endif 246 | |
247 //Make sure ticks are still on multiples of cycles 248 tickEvent.schedule(nextCycle(curTick + cycles(delay))); 249 _status = Running; 250} 251 252 253void 254AtomicSimpleCPU::suspendContext(int thread_num) --- 29 unchanged lines hidden (view full) --- 284 285 // translate to physical address 286 Fault fault = thread->translateDataReadReq(req); 287 288 // Now do the access. 289 if (fault == NoFault) { 290 pkt->reinitFromRequest(); 291 | 244 //Make sure ticks are still on multiples of cycles 245 tickEvent.schedule(nextCycle(curTick + cycles(delay))); 246 _status = Running; 247} 248 249 250void 251AtomicSimpleCPU::suspendContext(int thread_num) --- 29 unchanged lines hidden (view full) --- 281 282 // translate to physical address 283 Fault fault = thread->translateDataReadReq(req); 284 285 // Now do the access. 286 if (fault == NoFault) { 287 pkt->reinitFromRequest(); 288 |
292 dcache_latency = dcachePort.sendAtomic(pkt); | 289 if (req->isMmapedIpr()) 290 dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt); 291 else 292 dcache_latency = dcachePort.sendAtomic(pkt); |
293 dcache_access = true; 294 295 assert(pkt->result == Packet::Success); 296 data = pkt->get<T>(); 297 298 if (req->isLocked()) { 299 TheISA::handleLockedRead(thread, req); 300 } --- 70 unchanged lines hidden (view full) --- 371 if (fault == NoFault) { 372 bool do_access = true; // flag to suppress cache access 373 374 if (req->isLocked()) { 375 do_access = TheISA::handleLockedWrite(thread, req); 376 } 377 378 if (do_access) { | 293 dcache_access = true; 294 295 assert(pkt->result == Packet::Success); 296 data = pkt->get<T>(); 297 298 if (req->isLocked()) { 299 TheISA::handleLockedRead(thread, req); 300 } --- 70 unchanged lines hidden (view full) --- 371 if (fault == NoFault) { 372 bool do_access = true; // flag to suppress cache access 373 374 if (req->isLocked()) { 375 do_access = TheISA::handleLockedWrite(thread, req); 376 } 377 378 if (do_access) { |
379 data = htog(data); | |
380 pkt->reinitFromRequest(); 381 pkt->dataStatic(&data); 382 | 379 pkt->reinitFromRequest(); 380 pkt->dataStatic(&data); 381 |
383 dcache_latency = dcachePort.sendAtomic(pkt); | 382 if (req->isMmapedIpr()) { 383 dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt); 384 } else { 385 data = htog(data); 386 dcache_latency = dcachePort.sendAtomic(pkt); 387 } |
384 dcache_access = true; 385 386 assert(pkt->result == Packet::Success); 387 } 388 389 if (req->isLocked()) { 390 uint64_t scResult = req->getScResult(); 391 if (scResult != 0) { --- 221 unchanged lines hidden --- | 388 dcache_access = true; 389 390 assert(pkt->result == Packet::Success); 391 } 392 393 if (req->isLocked()) { 394 uint64_t scResult = req->getScResult(); 395 if (scResult != 0) { --- 221 unchanged lines hidden --- |