atomic.cc (11877:5ea85692a53e) | atomic.cc (12127:4207df055b0d) |
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1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2012-2013,2015 ARM Limited 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 50 unchanged lines hidden (view full) --- 59#include "params/AtomicSimpleCPU.hh" 60#include "sim/faults.hh" 61#include "sim/full_system.hh" 62#include "sim/system.hh" 63 64using namespace std; 65using namespace TheISA; 66 | 1/* 2 * Copyright 2014 Google, Inc. 3 * Copyright (c) 2012-2013,2015 ARM Limited 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 50 unchanged lines hidden (view full) --- 59#include "params/AtomicSimpleCPU.hh" 60#include "sim/faults.hh" 61#include "sim/full_system.hh" 62#include "sim/system.hh" 63 64using namespace std; 65using namespace TheISA; 66 |
67AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c) 68 : Event(CPU_Tick_Pri), cpu(c) 69{ 70} 71 72 | |
73void | 67void |
74AtomicSimpleCPU::TickEvent::process() 75{ 76 cpu->tick(); 77} 78 79const char * 80AtomicSimpleCPU::TickEvent::description() const 81{ 82 return "AtomicSimpleCPU tick"; 83} 84 85void | |
86AtomicSimpleCPU::init() 87{ 88 BaseSimpleCPU::init(); 89 90 int cid = threadContexts[0]->contextId(); 91 ifetch_req.setContext(cid); 92 data_read_req.setContext(cid); 93 data_write_req.setContext(cid); 94} 95 96AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) | 68AtomicSimpleCPU::init() 69{ 70 BaseSimpleCPU::init(); 71 72 int cid = threadContexts[0]->contextId(); 73 ifetch_req.setContext(cid); 74 data_read_req.setContext(cid); 75 data_write_req.setContext(cid); 76} 77 78AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p) |
97 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false), | 79 : BaseSimpleCPU(p), 80 tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick", 81 false, Event::CPU_Tick_Pri), 82 width(p->width), locked(false), |
98 simulate_data_stalls(p->simulate_data_stalls), 99 simulate_inst_stalls(p->simulate_inst_stalls), 100 icachePort(name() + ".icache_port", this), 101 dcachePort(name() + ".dcache_port", this), 102 fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 103 ppCommit(nullptr) 104{ 105 _status = Idle; --- 608 unchanged lines hidden --- | 83 simulate_data_stalls(p->simulate_data_stalls), 84 simulate_inst_stalls(p->simulate_inst_stalls), 85 icachePort(name() + ".icache_port", this), 86 dcachePort(name() + ".dcache_port", this), 87 fastmem(p->fastmem), dcache_access(false), dcache_latency(0), 88 ppCommit(nullptr) 89{ 90 _status = Idle; --- 608 unchanged lines hidden --- |