1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/atomic.hh"
35#include "mem/packet.hh"
36#include "mem/packet_access.hh"
37#include "sim/builder.hh"
38#include "sim/system.hh"
39
40using namespace std;
41using namespace TheISA;
42
43AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
44 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
45{
46}
47
48
49void
50AtomicSimpleCPU::TickEvent::process()
51{
52 cpu->tick();
53}
54
55const char *
56AtomicSimpleCPU::TickEvent::description()
57{
58 return "AtomicSimpleCPU tick event";
59}
60
61Port *
62AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
63{
64 if (if_name == "dcache_port")
65 return &dcachePort;
66 else if (if_name == "icache_port")
67 return &icachePort;
68 else
69 panic("No Such Port\n");
70}
71
72void
73AtomicSimpleCPU::init()
74{
75 BaseCPU::init();
76#if FULL_SYSTEM
77 for (int i = 0; i < threadContexts.size(); ++i) {
78 ThreadContext *tc = threadContexts[i];
79
80 // initialize the mem pointers
81 tc->init();
82
83 // initialize CPU, including PC
84 TheISA::initCPU(tc, tc->readCpuId());
85 }
86#endif
87}
88
89bool
90AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
91{
92 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
93 return true;
94}
95
96Tick
97AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
98{
99 //Snooping a coherence request, just return
100 return 0;
101}
102
103void
104AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
105{
106 //No internal storage to update, just return
107 return;
108}
109
110void
111AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
112{
113 if (status == RangeChange) {
114 if (!snoopRangeSent) {
115 snoopRangeSent = true;
116 sendStatusChange(Port::RangeChange);
117 }
118 return;
119 }
120
121 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
122}
123
124void
125AtomicSimpleCPU::CpuPort::recvRetry()
126{
127 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
128}
129
130
131AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
132 : BaseSimpleCPU(p), tickEvent(this),
133 width(p->width), simulate_stalls(p->simulate_stalls),
134 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
135{
136 _status = Idle;
137
138 icachePort.snoopRangeSent = false;
139 dcachePort.snoopRangeSent = false;
140
141 ifetch_req = new Request();
142 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
143 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
144 ifetch_pkt->dataStatic(&inst);
145
146 data_read_req = new Request();
147 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
148 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
149 Packet::Broadcast);
150 data_read_pkt->dataStatic(&dataReg);
151
152 data_write_req = new Request();
153 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
154 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
155 Packet::Broadcast);
156}
157
158
159AtomicSimpleCPU::~AtomicSimpleCPU()
160{
161}
162
163void
164AtomicSimpleCPU::serialize(ostream &os)
165{
166 SimObject::State so_state = SimObject::getState();
167 SERIALIZE_ENUM(so_state);
168 Status _status = status();
169 SERIALIZE_ENUM(_status);
170 BaseSimpleCPU::serialize(os);
171 nameOut(os, csprintf("%s.tickEvent", name()));
172 tickEvent.serialize(os);
173}
174
175void
176AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
177{
178 SimObject::State so_state;
179 UNSERIALIZE_ENUM(so_state);
180 UNSERIALIZE_ENUM(_status);
181 BaseSimpleCPU::unserialize(cp, section);
182 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
183}
184
185void
186AtomicSimpleCPU::resume()
187{
188 if (_status != SwitchedOut && _status != Idle) {
189 assert(system->getMemoryMode() == System::Atomic);
190
191 changeState(SimObject::Running);
192 if (thread->status() == ThreadContext::Active) {
193 if (!tickEvent.scheduled()) {
194 tickEvent.schedule(nextCycle());
195 }
196 }
197 }
198}
199
200void
201AtomicSimpleCPU::switchOut()
202{
203 assert(status() == Running || status() == Idle);
204 _status = SwitchedOut;
205
206 tickEvent.squash();
207}
208
209
210void
211AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
212{
213 BaseCPU::takeOverFrom(oldCPU);
214
215 assert(!tickEvent.scheduled());
216
217 // if any of this CPU's ThreadContexts are active, mark the CPU as
218 // running and schedule its tick event.
219 for (int i = 0; i < threadContexts.size(); ++i) {
220 ThreadContext *tc = threadContexts[i];
221 if (tc->status() == ThreadContext::Active && _status != Running) {
222 _status = Running;
223 tickEvent.schedule(nextCycle());
224 break;
225 }
226 }
227 if (_status != Running) {
228 _status = Idle;
229 }
230}
231
232
233void
234AtomicSimpleCPU::activateContext(int thread_num, int delay)
235{
236 assert(thread_num == 0);
237 assert(thread);
238
239 assert(_status == Idle);
240 assert(!tickEvent.scheduled());
241
242 notIdleFraction++;
243 //Make sure ticks are still on multiples of cycles
244 tickEvent.schedule(nextCycle(curTick + cycles(delay)));
245 _status = Running;
246}
247
248
249void
250AtomicSimpleCPU::suspendContext(int thread_num)
251{
252 assert(thread_num == 0);
253 assert(thread);
254
255 assert(_status == Running);
256
257 // tick event may not be scheduled if this gets called from inside
258 // an instruction's execution, e.g. "quiesce"
259 if (tickEvent.scheduled())
260 tickEvent.deschedule();
261
262 notIdleFraction--;
263 _status = Idle;
264}
265
266
267template <class T>
268Fault
269AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
270{
271 // use the CPU's statically allocated read request and packet objects
272 Request *req = data_read_req;
273 PacketPtr pkt = data_read_pkt;
274
275 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
276
277 if (traceData) {
278 traceData->setAddr(addr);
279 }
280
281 // translate to physical address
282 Fault fault = thread->translateDataReadReq(req);
283
284 // Now do the access.
285 if (fault == NoFault) {
286 pkt->reinitFromRequest();
287
288 dcache_latency = dcachePort.sendAtomic(pkt);
289 dcache_access = true;
290
291 assert(pkt->result == Packet::Success);
292 data = pkt->get<T>();
293
294 if (req->isLocked()) {
295 TheISA::handleLockedRead(thread, req);
296 }
297 }
298
299 // This will need a new way to tell if it has a dcache attached.
300 if (req->isUncacheable())
301 recordEvent("Uncached Read");
302
303 return fault;
304}
305
306#ifndef DOXYGEN_SHOULD_SKIP_THIS
307
308template
309Fault
310AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
311
312template
313Fault
314AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
315
316template
317Fault
318AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
319
320template
321Fault
322AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
323
324#endif //DOXYGEN_SHOULD_SKIP_THIS
325
326template<>
327Fault
328AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
329{
330 return read(addr, *(uint64_t*)&data, flags);
331}
332
333template<>
334Fault
335AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
336{
337 return read(addr, *(uint32_t*)&data, flags);
338}
339
340
341template<>
342Fault
343AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
344{
345 return read(addr, (uint32_t&)data, flags);
346}
347
348
349template <class T>
350Fault
351AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
352{
353 // use the CPU's statically allocated write request and packet objects
354 Request *req = data_write_req;
355 PacketPtr pkt = data_write_pkt;
356
357 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
358
359 if (traceData) {
360 traceData->setAddr(addr);
361 }
362
363 // translate to physical address
364 Fault fault = thread->translateDataWriteReq(req);
365
366 // Now do the access.
367 if (fault == NoFault) {
368 bool do_access = true; // flag to suppress cache access
369
370 if (req->isLocked()) {
371 do_access = TheISA::handleLockedWrite(thread, req);
372 }
373
374 if (do_access) {
375 data = htog(data);
376 pkt->reinitFromRequest();
377 pkt->dataStatic(&data);
378
379 dcache_latency = dcachePort.sendAtomic(pkt);
380 dcache_access = true;
381
382 assert(pkt->result == Packet::Success);
383 }
384
385 if (req->isLocked()) {
386 uint64_t scResult = req->getScResult();
387 if (scResult != 0) {
388 // clear failure counter
389 thread->setStCondFailures(0);
390 }
391 if (res) {
392 *res = req->getScResult();
393 }
394 }
395 }
396
397 // This will need a new way to tell if it's hooked up to a cache or not.
398 if (req->isUncacheable())
399 recordEvent("Uncached Write");
400
401 // If the write needs to have a fault on the access, consider calling
402 // changeStatus() and changing it to "bad addr write" or something.
403 return fault;
404}
405
406
407#ifndef DOXYGEN_SHOULD_SKIP_THIS
408template
409Fault
410AtomicSimpleCPU::write(uint64_t data, Addr addr,
411 unsigned flags, uint64_t *res);
412
413template
414Fault
415AtomicSimpleCPU::write(uint32_t data, Addr addr,
416 unsigned flags, uint64_t *res);
417
418template
419Fault
420AtomicSimpleCPU::write(uint16_t data, Addr addr,
421 unsigned flags, uint64_t *res);
422
423template
424Fault
425AtomicSimpleCPU::write(uint8_t data, Addr addr,
426 unsigned flags, uint64_t *res);
427
428#endif //DOXYGEN_SHOULD_SKIP_THIS
429
430template<>
431Fault
432AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
433{
434 return write(*(uint64_t*)&data, addr, flags, res);
435}
436
437template<>
438Fault
439AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
440{
441 return write(*(uint32_t*)&data, addr, flags, res);
442}
443
444
445template<>
446Fault
447AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
448{
449 return write((uint32_t)data, addr, flags, res);
450}
451
452
453void
454AtomicSimpleCPU::tick()
455{
456 Tick latency = cycles(1); // instruction takes one cycle by default
457
458 for (int i = 0; i < width; ++i) {
459 numCycles++;
460
461 if (!curStaticInst || !curStaticInst->isDelayedCommit())
462 checkForInterrupts();
463
464 Fault fault = setupFetchRequest(ifetch_req);
465
466 if (fault == NoFault) {
467 ifetch_pkt->reinitFromRequest();
468
469 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
470 // ifetch_req is initialized to read the instruction directly
471 // into the CPU object's inst field.
472
473 dcache_access = false; // assume no dcache access
474 preExecute();
475 fault = curStaticInst->execute(this, traceData);
476 postExecute();
477
478 if (simulate_stalls) {
479 Tick icache_stall = icache_latency - cycles(1);
480 Tick dcache_stall =
481 dcache_access ? dcache_latency - cycles(1) : 0;
482 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
483 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
484 latency += cycles(stall_cycles+1);
485 else
486 latency += cycles(stall_cycles);
487 }
488
489 }
490
491 advancePC(fault);
492 }
493
494 if (_status != Idle)
495 tickEvent.schedule(curTick + latency);
496}
497
498
499////////////////////////////////////////////////////////////////////////
500//
501// AtomicSimpleCPU Simulation Object
502//
503BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
504
505 Param<Counter> max_insts_any_thread;
506 Param<Counter> max_insts_all_threads;
507 Param<Counter> max_loads_any_thread;
508 Param<Counter> max_loads_all_threads;
509 Param<Tick> progress_interval;
510 SimObjectParam<System *> system;
511 Param<int> cpu_id;
512
513#if FULL_SYSTEM
514 SimObjectParam<TheISA::ITB *> itb;
515 SimObjectParam<TheISA::DTB *> dtb;
516 Param<Tick> profile;
517
518 Param<bool> do_quiesce;
519 Param<bool> do_checkpoint_insts;
520 Param<bool> do_statistics_insts;
521#else
522 SimObjectParam<Process *> workload;
523#endif // FULL_SYSTEM
524
525 Param<int> clock;
526 Param<int> phase;
527
528 Param<bool> defer_registration;
529 Param<int> width;
530 Param<bool> function_trace;
531 Param<Tick> function_trace_start;
532 Param<bool> simulate_stalls;
533
534END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
535
536BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
537
538 INIT_PARAM(max_insts_any_thread,
539 "terminate when any thread reaches this inst count"),
540 INIT_PARAM(max_insts_all_threads,
541 "terminate when all threads have reached this inst count"),
542 INIT_PARAM(max_loads_any_thread,
543 "terminate when any thread reaches this load count"),
544 INIT_PARAM(max_loads_all_threads,
545 "terminate when all threads have reached this load count"),
546 INIT_PARAM(progress_interval, "Progress interval"),
547 INIT_PARAM(system, "system object"),
548 INIT_PARAM(cpu_id, "processor ID"),
549
550#if FULL_SYSTEM
551 INIT_PARAM(itb, "Instruction TLB"),
552 INIT_PARAM(dtb, "Data TLB"),
553 INIT_PARAM(profile, ""),
554 INIT_PARAM(do_quiesce, ""),
555 INIT_PARAM(do_checkpoint_insts, ""),
556 INIT_PARAM(do_statistics_insts, ""),
557#else
558 INIT_PARAM(workload, "processes to run"),
559#endif // FULL_SYSTEM
560
561 INIT_PARAM(clock, "clock speed"),
562 INIT_PARAM_DFLT(phase, "clock phase", 0),
563 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
564 INIT_PARAM(width, "cpu width"),
565 INIT_PARAM(function_trace, "Enable function trace"),
566 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
567 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
568
569END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
570
571
572CREATE_SIM_OBJECT(AtomicSimpleCPU)
573{
574 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
575 params->name = getInstanceName();
576 params->numberOfThreads = 1;
577 params->max_insts_any_thread = max_insts_any_thread;
578 params->max_insts_all_threads = max_insts_all_threads;
579 params->max_loads_any_thread = max_loads_any_thread;
580 params->max_loads_all_threads = max_loads_all_threads;
581 params->progress_interval = progress_interval;
582 params->deferRegistration = defer_registration;
583 params->phase = phase;
584 params->clock = clock;
585 params->functionTrace = function_trace;
586 params->functionTraceStart = function_trace_start;
587 params->width = width;
588 params->simulate_stalls = simulate_stalls;
589 params->system = system;
590 params->cpu_id = cpu_id;
591
592#if FULL_SYSTEM
593 params->itb = itb;
594 params->dtb = dtb;
595 params->profile = profile;
596 params->do_quiesce = do_quiesce;
597 params->do_checkpoint_insts = do_checkpoint_insts;
598 params->do_statistics_insts = do_statistics_insts;
599#else
600 params->process = workload;
601#endif
602
603 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
604 return cpu;
605}
606
607REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
608
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "cpu/exetrace.hh"
34#include "cpu/simple/atomic.hh"
35#include "mem/packet.hh"
36#include "mem/packet_access.hh"
37#include "sim/builder.hh"
38#include "sim/system.hh"
39
40using namespace std;
41using namespace TheISA;
42
43AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
44 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
45{
46}
47
48
49void
50AtomicSimpleCPU::TickEvent::process()
51{
52 cpu->tick();
53}
54
55const char *
56AtomicSimpleCPU::TickEvent::description()
57{
58 return "AtomicSimpleCPU tick event";
59}
60
61Port *
62AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
63{
64 if (if_name == "dcache_port")
65 return &dcachePort;
66 else if (if_name == "icache_port")
67 return &icachePort;
68 else
69 panic("No Such Port\n");
70}
71
72void
73AtomicSimpleCPU::init()
74{
75 BaseCPU::init();
76#if FULL_SYSTEM
77 for (int i = 0; i < threadContexts.size(); ++i) {
78 ThreadContext *tc = threadContexts[i];
79
80 // initialize the mem pointers
81 tc->init();
82
83 // initialize CPU, including PC
84 TheISA::initCPU(tc, tc->readCpuId());
85 }
86#endif
87}
88
89bool
90AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
91{
92 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
93 return true;
94}
95
96Tick
97AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
98{
99 //Snooping a coherence request, just return
100 return 0;
101}
102
103void
104AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
105{
106 //No internal storage to update, just return
107 return;
108}
109
110void
111AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
112{
113 if (status == RangeChange) {
114 if (!snoopRangeSent) {
115 snoopRangeSent = true;
116 sendStatusChange(Port::RangeChange);
117 }
118 return;
119 }
120
121 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
122}
123
124void
125AtomicSimpleCPU::CpuPort::recvRetry()
126{
127 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
128}
129
130
131AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
132 : BaseSimpleCPU(p), tickEvent(this),
133 width(p->width), simulate_stalls(p->simulate_stalls),
134 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
135{
136 _status = Idle;
137
138 icachePort.snoopRangeSent = false;
139 dcachePort.snoopRangeSent = false;
140
141 ifetch_req = new Request();
142 ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
143 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
144 ifetch_pkt->dataStatic(&inst);
145
146 data_read_req = new Request();
147 data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
148 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
149 Packet::Broadcast);
150 data_read_pkt->dataStatic(&dataReg);
151
152 data_write_req = new Request();
153 data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
154 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
155 Packet::Broadcast);
156}
157
158
159AtomicSimpleCPU::~AtomicSimpleCPU()
160{
161}
162
163void
164AtomicSimpleCPU::serialize(ostream &os)
165{
166 SimObject::State so_state = SimObject::getState();
167 SERIALIZE_ENUM(so_state);
168 Status _status = status();
169 SERIALIZE_ENUM(_status);
170 BaseSimpleCPU::serialize(os);
171 nameOut(os, csprintf("%s.tickEvent", name()));
172 tickEvent.serialize(os);
173}
174
175void
176AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
177{
178 SimObject::State so_state;
179 UNSERIALIZE_ENUM(so_state);
180 UNSERIALIZE_ENUM(_status);
181 BaseSimpleCPU::unserialize(cp, section);
182 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
183}
184
185void
186AtomicSimpleCPU::resume()
187{
188 if (_status != SwitchedOut && _status != Idle) {
189 assert(system->getMemoryMode() == System::Atomic);
190
191 changeState(SimObject::Running);
192 if (thread->status() == ThreadContext::Active) {
193 if (!tickEvent.scheduled()) {
194 tickEvent.schedule(nextCycle());
195 }
196 }
197 }
198}
199
200void
201AtomicSimpleCPU::switchOut()
202{
203 assert(status() == Running || status() == Idle);
204 _status = SwitchedOut;
205
206 tickEvent.squash();
207}
208
209
210void
211AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
212{
213 BaseCPU::takeOverFrom(oldCPU);
214
215 assert(!tickEvent.scheduled());
216
217 // if any of this CPU's ThreadContexts are active, mark the CPU as
218 // running and schedule its tick event.
219 for (int i = 0; i < threadContexts.size(); ++i) {
220 ThreadContext *tc = threadContexts[i];
221 if (tc->status() == ThreadContext::Active && _status != Running) {
222 _status = Running;
223 tickEvent.schedule(nextCycle());
224 break;
225 }
226 }
227 if (_status != Running) {
228 _status = Idle;
229 }
230}
231
232
233void
234AtomicSimpleCPU::activateContext(int thread_num, int delay)
235{
236 assert(thread_num == 0);
237 assert(thread);
238
239 assert(_status == Idle);
240 assert(!tickEvent.scheduled());
241
242 notIdleFraction++;
243 //Make sure ticks are still on multiples of cycles
244 tickEvent.schedule(nextCycle(curTick + cycles(delay)));
245 _status = Running;
246}
247
248
249void
250AtomicSimpleCPU::suspendContext(int thread_num)
251{
252 assert(thread_num == 0);
253 assert(thread);
254
255 assert(_status == Running);
256
257 // tick event may not be scheduled if this gets called from inside
258 // an instruction's execution, e.g. "quiesce"
259 if (tickEvent.scheduled())
260 tickEvent.deschedule();
261
262 notIdleFraction--;
263 _status = Idle;
264}
265
266
267template <class T>
268Fault
269AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
270{
271 // use the CPU's statically allocated read request and packet objects
272 Request *req = data_read_req;
273 PacketPtr pkt = data_read_pkt;
274
275 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
276
277 if (traceData) {
278 traceData->setAddr(addr);
279 }
280
281 // translate to physical address
282 Fault fault = thread->translateDataReadReq(req);
283
284 // Now do the access.
285 if (fault == NoFault) {
286 pkt->reinitFromRequest();
287
288 dcache_latency = dcachePort.sendAtomic(pkt);
289 dcache_access = true;
290
291 assert(pkt->result == Packet::Success);
292 data = pkt->get<T>();
293
294 if (req->isLocked()) {
295 TheISA::handleLockedRead(thread, req);
296 }
297 }
298
299 // This will need a new way to tell if it has a dcache attached.
300 if (req->isUncacheable())
301 recordEvent("Uncached Read");
302
303 return fault;
304}
305
306#ifndef DOXYGEN_SHOULD_SKIP_THIS
307
308template
309Fault
310AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
311
312template
313Fault
314AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
315
316template
317Fault
318AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
319
320template
321Fault
322AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
323
324#endif //DOXYGEN_SHOULD_SKIP_THIS
325
326template<>
327Fault
328AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
329{
330 return read(addr, *(uint64_t*)&data, flags);
331}
332
333template<>
334Fault
335AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
336{
337 return read(addr, *(uint32_t*)&data, flags);
338}
339
340
341template<>
342Fault
343AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
344{
345 return read(addr, (uint32_t&)data, flags);
346}
347
348
349template <class T>
350Fault
351AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
352{
353 // use the CPU's statically allocated write request and packet objects
354 Request *req = data_write_req;
355 PacketPtr pkt = data_write_pkt;
356
357 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
358
359 if (traceData) {
360 traceData->setAddr(addr);
361 }
362
363 // translate to physical address
364 Fault fault = thread->translateDataWriteReq(req);
365
366 // Now do the access.
367 if (fault == NoFault) {
368 bool do_access = true; // flag to suppress cache access
369
370 if (req->isLocked()) {
371 do_access = TheISA::handleLockedWrite(thread, req);
372 }
373
374 if (do_access) {
375 data = htog(data);
376 pkt->reinitFromRequest();
377 pkt->dataStatic(&data);
378
379 dcache_latency = dcachePort.sendAtomic(pkt);
380 dcache_access = true;
381
382 assert(pkt->result == Packet::Success);
383 }
384
385 if (req->isLocked()) {
386 uint64_t scResult = req->getScResult();
387 if (scResult != 0) {
388 // clear failure counter
389 thread->setStCondFailures(0);
390 }
391 if (res) {
392 *res = req->getScResult();
393 }
394 }
395 }
396
397 // This will need a new way to tell if it's hooked up to a cache or not.
398 if (req->isUncacheable())
399 recordEvent("Uncached Write");
400
401 // If the write needs to have a fault on the access, consider calling
402 // changeStatus() and changing it to "bad addr write" or something.
403 return fault;
404}
405
406
407#ifndef DOXYGEN_SHOULD_SKIP_THIS
408template
409Fault
410AtomicSimpleCPU::write(uint64_t data, Addr addr,
411 unsigned flags, uint64_t *res);
412
413template
414Fault
415AtomicSimpleCPU::write(uint32_t data, Addr addr,
416 unsigned flags, uint64_t *res);
417
418template
419Fault
420AtomicSimpleCPU::write(uint16_t data, Addr addr,
421 unsigned flags, uint64_t *res);
422
423template
424Fault
425AtomicSimpleCPU::write(uint8_t data, Addr addr,
426 unsigned flags, uint64_t *res);
427
428#endif //DOXYGEN_SHOULD_SKIP_THIS
429
430template<>
431Fault
432AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
433{
434 return write(*(uint64_t*)&data, addr, flags, res);
435}
436
437template<>
438Fault
439AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
440{
441 return write(*(uint32_t*)&data, addr, flags, res);
442}
443
444
445template<>
446Fault
447AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
448{
449 return write((uint32_t)data, addr, flags, res);
450}
451
452
453void
454AtomicSimpleCPU::tick()
455{
456 Tick latency = cycles(1); // instruction takes one cycle by default
457
458 for (int i = 0; i < width; ++i) {
459 numCycles++;
460
461 if (!curStaticInst || !curStaticInst->isDelayedCommit())
462 checkForInterrupts();
463
464 Fault fault = setupFetchRequest(ifetch_req);
465
466 if (fault == NoFault) {
467 ifetch_pkt->reinitFromRequest();
468
469 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
470 // ifetch_req is initialized to read the instruction directly
471 // into the CPU object's inst field.
472
473 dcache_access = false; // assume no dcache access
474 preExecute();
475 fault = curStaticInst->execute(this, traceData);
476 postExecute();
477
478 if (simulate_stalls) {
479 Tick icache_stall = icache_latency - cycles(1);
480 Tick dcache_stall =
481 dcache_access ? dcache_latency - cycles(1) : 0;
482 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
483 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
484 latency += cycles(stall_cycles+1);
485 else
486 latency += cycles(stall_cycles);
487 }
488
489 }
490
491 advancePC(fault);
492 }
493
494 if (_status != Idle)
495 tickEvent.schedule(curTick + latency);
496}
497
498
499////////////////////////////////////////////////////////////////////////
500//
501// AtomicSimpleCPU Simulation Object
502//
503BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
504
505 Param<Counter> max_insts_any_thread;
506 Param<Counter> max_insts_all_threads;
507 Param<Counter> max_loads_any_thread;
508 Param<Counter> max_loads_all_threads;
509 Param<Tick> progress_interval;
510 SimObjectParam<System *> system;
511 Param<int> cpu_id;
512
513#if FULL_SYSTEM
514 SimObjectParam<TheISA::ITB *> itb;
515 SimObjectParam<TheISA::DTB *> dtb;
516 Param<Tick> profile;
517
518 Param<bool> do_quiesce;
519 Param<bool> do_checkpoint_insts;
520 Param<bool> do_statistics_insts;
521#else
522 SimObjectParam<Process *> workload;
523#endif // FULL_SYSTEM
524
525 Param<int> clock;
526 Param<int> phase;
527
528 Param<bool> defer_registration;
529 Param<int> width;
530 Param<bool> function_trace;
531 Param<Tick> function_trace_start;
532 Param<bool> simulate_stalls;
533
534END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
535
536BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
537
538 INIT_PARAM(max_insts_any_thread,
539 "terminate when any thread reaches this inst count"),
540 INIT_PARAM(max_insts_all_threads,
541 "terminate when all threads have reached this inst count"),
542 INIT_PARAM(max_loads_any_thread,
543 "terminate when any thread reaches this load count"),
544 INIT_PARAM(max_loads_all_threads,
545 "terminate when all threads have reached this load count"),
546 INIT_PARAM(progress_interval, "Progress interval"),
547 INIT_PARAM(system, "system object"),
548 INIT_PARAM(cpu_id, "processor ID"),
549
550#if FULL_SYSTEM
551 INIT_PARAM(itb, "Instruction TLB"),
552 INIT_PARAM(dtb, "Data TLB"),
553 INIT_PARAM(profile, ""),
554 INIT_PARAM(do_quiesce, ""),
555 INIT_PARAM(do_checkpoint_insts, ""),
556 INIT_PARAM(do_statistics_insts, ""),
557#else
558 INIT_PARAM(workload, "processes to run"),
559#endif // FULL_SYSTEM
560
561 INIT_PARAM(clock, "clock speed"),
562 INIT_PARAM_DFLT(phase, "clock phase", 0),
563 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
564 INIT_PARAM(width, "cpu width"),
565 INIT_PARAM(function_trace, "Enable function trace"),
566 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
567 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
568
569END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
570
571
572CREATE_SIM_OBJECT(AtomicSimpleCPU)
573{
574 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
575 params->name = getInstanceName();
576 params->numberOfThreads = 1;
577 params->max_insts_any_thread = max_insts_any_thread;
578 params->max_insts_all_threads = max_insts_all_threads;
579 params->max_loads_any_thread = max_loads_any_thread;
580 params->max_loads_all_threads = max_loads_all_threads;
581 params->progress_interval = progress_interval;
582 params->deferRegistration = defer_registration;
583 params->phase = phase;
584 params->clock = clock;
585 params->functionTrace = function_trace;
586 params->functionTraceStart = function_trace_start;
587 params->width = width;
588 params->simulate_stalls = simulate_stalls;
589 params->system = system;
590 params->cpu_id = cpu_id;
591
592#if FULL_SYSTEM
593 params->itb = itb;
594 params->dtb = dtb;
595 params->profile = profile;
596 params->do_quiesce = do_quiesce;
597 params->do_checkpoint_insts = do_checkpoint_insts;
598 params->do_statistics_insts = do_statistics_insts;
599#else
600 params->process = workload;
601#endif
602
603 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
604 return cpu;
605}
606
607REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
608