1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/atomic.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36#include "sim/system.hh"
37
38using namespace std;
39using namespace TheISA;
40
41AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
42 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
43{
44}
45
46
47void
48AtomicSimpleCPU::TickEvent::process()
49{
50 cpu->tick();
51}
52
53const char *
54AtomicSimpleCPU::TickEvent::description()
55{
56 return "AtomicSimpleCPU tick event";
57}
58
59Port *
60AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
61{
62 if (if_name == "dcache_port")
63 return &dcachePort;
64 else if (if_name == "icache_port")
65 return &icachePort;
66 else
67 panic("No Such Port\n");
68}
69
70void
71AtomicSimpleCPU::init()
72{
73 //Create Memory Ports (conect them up)
74// Port *mem_dport = mem->getPort("");
75// dcachePort.setPeer(mem_dport);
76// mem_dport->setPeer(&dcachePort);
77
78// Port *mem_iport = mem->getPort("");
79// icachePort.setPeer(mem_iport);
80// mem_iport->setPeer(&icachePort);
81
82 BaseCPU::init();
83#if FULL_SYSTEM
84 for (int i = 0; i < threadContexts.size(); ++i) {
85 ThreadContext *tc = threadContexts[i];
86
87 // initialize CPU, including PC
88 TheISA::initCPU(tc, tc->readCpuId());
89 }
90#endif
91}
92
93bool
94AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
95{
96 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
97 return true;
98}
99
100Tick
101AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
102{
103 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
104 return curTick;
105}
106
107void
108AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
109{
110 panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
111}
112
113void
114AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
115{
116 if (status == RangeChange)
117 return;
118
119 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
120}
121
122void
123AtomicSimpleCPU::CpuPort::recvRetry()
124{
125 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
126}
127
128
129AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
130 : BaseSimpleCPU(p), tickEvent(this),
131 width(p->width), simulate_stalls(p->simulate_stalls),
132 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
133{
134 _status = Idle;
135
136 // @todo fix me and get the real cpu id & thread number!!!
137 ifetch_req = new Request();
138 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
139 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
140 ifetch_pkt->dataStatic(&inst);
141
142 data_read_req = new Request();
143 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
144 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
145 Packet::Broadcast);
146 data_read_pkt->dataStatic(&dataReg);
147
148 data_write_req = new Request();
149 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
150 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
151 Packet::Broadcast);
152}
153
154
155AtomicSimpleCPU::~AtomicSimpleCPU()
156{
157}
158
159void
160AtomicSimpleCPU::serialize(ostream &os)
161{
162 SimObject::State so_state = SimObject::getState();
163 SERIALIZE_ENUM(so_state);
164 BaseSimpleCPU::serialize(os);
165 nameOut(os, csprintf("%s.tickEvent", name()));
166 tickEvent.serialize(os);
167}
168
169void
170AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
171{
172 SimObject::State so_state;
173 UNSERIALIZE_ENUM(so_state);
174 BaseSimpleCPU::unserialize(cp, section);
175 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
176}
177
178void
179AtomicSimpleCPU::resume()
180{
181 assert(system->getMemoryMode() == System::Atomic);
182 changeState(SimObject::Running);
183 if (thread->status() == ThreadContext::Active) {
184 if (!tickEvent.scheduled())
185 tickEvent.schedule(curTick);
186 }
187}
188
189void
190AtomicSimpleCPU::switchOut()
191{
192 assert(status() == Running || status() == Idle);
193 _status = SwitchedOut;
194
195 tickEvent.squash();
196}
197
198
199void
200AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
201{
202 BaseCPU::takeOverFrom(oldCPU);
203
204 assert(!tickEvent.scheduled());
205
206 // if any of this CPU's ThreadContexts are active, mark the CPU as
207 // running and schedule its tick event.
208 for (int i = 0; i < threadContexts.size(); ++i) {
209 ThreadContext *tc = threadContexts[i];
210 if (tc->status() == ThreadContext::Active && _status != Running) {
211 _status = Running;
212 tickEvent.schedule(curTick);
213 break;
214 }
215 }
216}
217
218
219void
220AtomicSimpleCPU::activateContext(int thread_num, int delay)
221{
222 assert(thread_num == 0);
223 assert(thread);
224
225 assert(_status == Idle);
226 assert(!tickEvent.scheduled());
227
228 notIdleFraction++;
229 tickEvent.schedule(curTick + cycles(delay));
230 _status = Running;
231}
232
233
234void
235AtomicSimpleCPU::suspendContext(int thread_num)
236{
237 assert(thread_num == 0);
238 assert(thread);
239
240 assert(_status == Running);
241
242 // tick event may not be scheduled if this gets called from inside
243 // an instruction's execution, e.g. "quiesce"
244 if (tickEvent.scheduled())
245 tickEvent.deschedule();
246
247 notIdleFraction--;
248 _status = Idle;
249}
250
251
252template <class T>
253Fault
254AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
255{
256 // use the CPU's statically allocated read request and packet objects
257 Request *req = data_read_req;
258 Packet *pkt = data_read_pkt;
259
260 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
261
262 if (traceData) {
263 traceData->setAddr(addr);
264 }
265
266 // translate to physical address
267 Fault fault = thread->translateDataReadReq(req);
268
269 // Now do the access.
270 if (fault == NoFault) {
271 pkt->reinitFromRequest();
272
273 dcache_latency = dcachePort.sendAtomic(pkt);
274 dcache_access = true;
275
276 assert(pkt->result == Packet::Success);
277 data = pkt->get<T>();
278 }
279
280 // This will need a new way to tell if it has a dcache attached.
281 if (req->getFlags() & UNCACHEABLE)
282 recordEvent("Uncached Read");
283
284 return fault;
285}
286
287#ifndef DOXYGEN_SHOULD_SKIP_THIS
288
289template
290Fault
291AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
292
293template
294Fault
295AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
296
297template
298Fault
299AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
300
301template
302Fault
303AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
304
305#endif //DOXYGEN_SHOULD_SKIP_THIS
306
307template<>
308Fault
309AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
310{
311 return read(addr, *(uint64_t*)&data, flags);
312}
313
314template<>
315Fault
316AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
317{
318 return read(addr, *(uint32_t*)&data, flags);
319}
320
321
322template<>
323Fault
324AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
325{
326 return read(addr, (uint32_t&)data, flags);
327}
328
329
330template <class T>
331Fault
332AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
333{
334 // use the CPU's statically allocated write request and packet objects
335 Request *req = data_write_req;
336 Packet *pkt = data_write_pkt;
337
338 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
339
340 if (traceData) {
341 traceData->setAddr(addr);
342 }
343
344 // translate to physical address
345 Fault fault = thread->translateDataWriteReq(req);
346
347 // Now do the access.
348 if (fault == NoFault) {
349 data = htog(data);
350 pkt->reinitFromRequest();
351 pkt->dataStatic(&data);
352
353 dcache_latency = dcachePort.sendAtomic(pkt);
354 dcache_access = true;
355
356 assert(pkt->result == Packet::Success);
357
358 if (res && req->getFlags() & LOCKED) {
359 *res = req->getScResult();
360 }
361 }
362
363 // This will need a new way to tell if it's hooked up to a cache or not.
364 if (req->getFlags() & UNCACHEABLE)
365 recordEvent("Uncached Write");
366
367 // If the write needs to have a fault on the access, consider calling
368 // changeStatus() and changing it to "bad addr write" or something.
369 return fault;
370}
371
372
373#ifndef DOXYGEN_SHOULD_SKIP_THIS
374template
375Fault
376AtomicSimpleCPU::write(uint64_t data, Addr addr,
377 unsigned flags, uint64_t *res);
378
379template
380Fault
381AtomicSimpleCPU::write(uint32_t data, Addr addr,
382 unsigned flags, uint64_t *res);
383
384template
385Fault
386AtomicSimpleCPU::write(uint16_t data, Addr addr,
387 unsigned flags, uint64_t *res);
388
389template
390Fault
391AtomicSimpleCPU::write(uint8_t data, Addr addr,
392 unsigned flags, uint64_t *res);
393
394#endif //DOXYGEN_SHOULD_SKIP_THIS
395
396template<>
397Fault
398AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
399{
400 return write(*(uint64_t*)&data, addr, flags, res);
401}
402
403template<>
404Fault
405AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
406{
407 return write(*(uint32_t*)&data, addr, flags, res);
408}
409
410
411template<>
412Fault
413AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
414{
415 return write((uint32_t)data, addr, flags, res);
416}
417
418
419void
420AtomicSimpleCPU::tick()
421{
422 Tick latency = cycles(1); // instruction takes one cycle by default
423
424 for (int i = 0; i < width; ++i) {
425 numCycles++;
426
427 checkForInterrupts();
428
429 Fault fault = setupFetchRequest(ifetch_req);
430
431 if (fault == NoFault) {
432 ifetch_pkt->reinitFromRequest();
433
434 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
435 // ifetch_req is initialized to read the instruction directly
436 // into the CPU object's inst field.
437
438 dcache_access = false; // assume no dcache access
439 preExecute();
440 fault = curStaticInst->execute(this, traceData);
441 postExecute();
442
443 if (simulate_stalls) {
444 Tick icache_stall = icache_latency - cycles(1);
445 Tick dcache_stall =
446 dcache_access ? dcache_latency - cycles(1) : 0;
447 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
448 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
449 latency += cycles(stall_cycles+1);
450 else
451 latency += cycles(stall_cycles);
452 }
453
454 }
455
456 advancePC(fault);
457 }
458
459 if (_status != Idle)
460 tickEvent.schedule(curTick + latency);
461}
462
463
464////////////////////////////////////////////////////////////////////////
465//
466// AtomicSimpleCPU Simulation Object
467//
468BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
469
470 Param<Counter> max_insts_any_thread;
471 Param<Counter> max_insts_all_threads;
472 Param<Counter> max_loads_any_thread;
473 Param<Counter> max_loads_all_threads;
474 Param<Tick> progress_interval;
475 SimObjectParam<MemObject *> mem;
476 SimObjectParam<System *> system;
477
478#if FULL_SYSTEM
479 SimObjectParam<AlphaITB *> itb;
480 SimObjectParam<AlphaDTB *> dtb;
481 Param<int> cpu_id;
482 Param<Tick> profile;
483#else
484 SimObjectParam<Process *> workload;
485#endif // FULL_SYSTEM
486
487 Param<int> clock;
488
489 Param<bool> defer_registration;
490 Param<int> width;
491 Param<bool> function_trace;
492 Param<Tick> function_trace_start;
493 Param<bool> simulate_stalls;
494
495END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
496
497BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
498
499 INIT_PARAM(max_insts_any_thread,
500 "terminate when any thread reaches this inst count"),
501 INIT_PARAM(max_insts_all_threads,
502 "terminate when all threads have reached this inst count"),
503 INIT_PARAM(max_loads_any_thread,
504 "terminate when any thread reaches this load count"),
505 INIT_PARAM(max_loads_all_threads,
506 "terminate when all threads have reached this load count"),
507 INIT_PARAM(progress_interval, "Progress interval"),
508 INIT_PARAM(mem, "memory"),
509 INIT_PARAM(system, "system object"),
510
511#if FULL_SYSTEM
512 INIT_PARAM(itb, "Instruction TLB"),
513 INIT_PARAM(dtb, "Data TLB"),
514 INIT_PARAM(cpu_id, "processor ID"),
515 INIT_PARAM(profile, ""),
516#else
517 INIT_PARAM(workload, "processes to run"),
518#endif // FULL_SYSTEM
519
520 INIT_PARAM(clock, "clock speed"),
521 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
522 INIT_PARAM(width, "cpu width"),
523 INIT_PARAM(function_trace, "Enable function trace"),
524 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
525 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
526
527END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
528
529
530CREATE_SIM_OBJECT(AtomicSimpleCPU)
531{
532 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
533 params->name = getInstanceName();
534 params->numberOfThreads = 1;
535 params->max_insts_any_thread = max_insts_any_thread;
536 params->max_insts_all_threads = max_insts_all_threads;
537 params->max_loads_any_thread = max_loads_any_thread;
538 params->max_loads_all_threads = max_loads_all_threads;
539 params->progress_interval = progress_interval;
540 params->deferRegistration = defer_registration;
541 params->clock = clock;
542 params->functionTrace = function_trace;
543 params->functionTraceStart = function_trace_start;
544 params->width = width;
545 params->simulate_stalls = simulate_stalls;
546 params->mem = mem;
547 params->system = system;
548
549#if FULL_SYSTEM
550 params->itb = itb;
551 params->dtb = dtb;
552 params->cpu_id = cpu_id;
553 params->profile = profile;
554#else
555 params->process = workload;
556#endif
557
558 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
559 return cpu;
560}
561
562REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
563
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/atomic.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36#include "sim/system.hh"
37
38using namespace std;
39using namespace TheISA;
40
41AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
42 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
43{
44}
45
46
47void
48AtomicSimpleCPU::TickEvent::process()
49{
50 cpu->tick();
51}
52
53const char *
54AtomicSimpleCPU::TickEvent::description()
55{
56 return "AtomicSimpleCPU tick event";
57}
58
59Port *
60AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
61{
62 if (if_name == "dcache_port")
63 return &dcachePort;
64 else if (if_name == "icache_port")
65 return &icachePort;
66 else
67 panic("No Such Port\n");
68}
69
70void
71AtomicSimpleCPU::init()
72{
73 //Create Memory Ports (conect them up)
74// Port *mem_dport = mem->getPort("");
75// dcachePort.setPeer(mem_dport);
76// mem_dport->setPeer(&dcachePort);
77
78// Port *mem_iport = mem->getPort("");
79// icachePort.setPeer(mem_iport);
80// mem_iport->setPeer(&icachePort);
81
82 BaseCPU::init();
83#if FULL_SYSTEM
84 for (int i = 0; i < threadContexts.size(); ++i) {
85 ThreadContext *tc = threadContexts[i];
86
87 // initialize CPU, including PC
88 TheISA::initCPU(tc, tc->readCpuId());
89 }
90#endif
91}
92
93bool
94AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
95{
96 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
97 return true;
98}
99
100Tick
101AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
102{
103 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
104 return curTick;
105}
106
107void
108AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
109{
110 panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
111}
112
113void
114AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
115{
116 if (status == RangeChange)
117 return;
118
119 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
120}
121
122void
123AtomicSimpleCPU::CpuPort::recvRetry()
124{
125 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
126}
127
128
129AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
130 : BaseSimpleCPU(p), tickEvent(this),
131 width(p->width), simulate_stalls(p->simulate_stalls),
132 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
133{
134 _status = Idle;
135
136 // @todo fix me and get the real cpu id & thread number!!!
137 ifetch_req = new Request();
138 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
139 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
140 ifetch_pkt->dataStatic(&inst);
141
142 data_read_req = new Request();
143 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
144 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
145 Packet::Broadcast);
146 data_read_pkt->dataStatic(&dataReg);
147
148 data_write_req = new Request();
149 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
150 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
151 Packet::Broadcast);
152}
153
154
155AtomicSimpleCPU::~AtomicSimpleCPU()
156{
157}
158
159void
160AtomicSimpleCPU::serialize(ostream &os)
161{
162 SimObject::State so_state = SimObject::getState();
163 SERIALIZE_ENUM(so_state);
164 BaseSimpleCPU::serialize(os);
165 nameOut(os, csprintf("%s.tickEvent", name()));
166 tickEvent.serialize(os);
167}
168
169void
170AtomicSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
171{
172 SimObject::State so_state;
173 UNSERIALIZE_ENUM(so_state);
174 BaseSimpleCPU::unserialize(cp, section);
175 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
176}
177
178void
179AtomicSimpleCPU::resume()
180{
181 assert(system->getMemoryMode() == System::Atomic);
182 changeState(SimObject::Running);
183 if (thread->status() == ThreadContext::Active) {
184 if (!tickEvent.scheduled())
185 tickEvent.schedule(curTick);
186 }
187}
188
189void
190AtomicSimpleCPU::switchOut()
191{
192 assert(status() == Running || status() == Idle);
193 _status = SwitchedOut;
194
195 tickEvent.squash();
196}
197
198
199void
200AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
201{
202 BaseCPU::takeOverFrom(oldCPU);
203
204 assert(!tickEvent.scheduled());
205
206 // if any of this CPU's ThreadContexts are active, mark the CPU as
207 // running and schedule its tick event.
208 for (int i = 0; i < threadContexts.size(); ++i) {
209 ThreadContext *tc = threadContexts[i];
210 if (tc->status() == ThreadContext::Active && _status != Running) {
211 _status = Running;
212 tickEvent.schedule(curTick);
213 break;
214 }
215 }
216}
217
218
219void
220AtomicSimpleCPU::activateContext(int thread_num, int delay)
221{
222 assert(thread_num == 0);
223 assert(thread);
224
225 assert(_status == Idle);
226 assert(!tickEvent.scheduled());
227
228 notIdleFraction++;
229 tickEvent.schedule(curTick + cycles(delay));
230 _status = Running;
231}
232
233
234void
235AtomicSimpleCPU::suspendContext(int thread_num)
236{
237 assert(thread_num == 0);
238 assert(thread);
239
240 assert(_status == Running);
241
242 // tick event may not be scheduled if this gets called from inside
243 // an instruction's execution, e.g. "quiesce"
244 if (tickEvent.scheduled())
245 tickEvent.deschedule();
246
247 notIdleFraction--;
248 _status = Idle;
249}
250
251
252template <class T>
253Fault
254AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
255{
256 // use the CPU's statically allocated read request and packet objects
257 Request *req = data_read_req;
258 Packet *pkt = data_read_pkt;
259
260 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
261
262 if (traceData) {
263 traceData->setAddr(addr);
264 }
265
266 // translate to physical address
267 Fault fault = thread->translateDataReadReq(req);
268
269 // Now do the access.
270 if (fault == NoFault) {
271 pkt->reinitFromRequest();
272
273 dcache_latency = dcachePort.sendAtomic(pkt);
274 dcache_access = true;
275
276 assert(pkt->result == Packet::Success);
277 data = pkt->get<T>();
278 }
279
280 // This will need a new way to tell if it has a dcache attached.
281 if (req->getFlags() & UNCACHEABLE)
282 recordEvent("Uncached Read");
283
284 return fault;
285}
286
287#ifndef DOXYGEN_SHOULD_SKIP_THIS
288
289template
290Fault
291AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
292
293template
294Fault
295AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
296
297template
298Fault
299AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
300
301template
302Fault
303AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
304
305#endif //DOXYGEN_SHOULD_SKIP_THIS
306
307template<>
308Fault
309AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
310{
311 return read(addr, *(uint64_t*)&data, flags);
312}
313
314template<>
315Fault
316AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
317{
318 return read(addr, *(uint32_t*)&data, flags);
319}
320
321
322template<>
323Fault
324AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
325{
326 return read(addr, (uint32_t&)data, flags);
327}
328
329
330template <class T>
331Fault
332AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
333{
334 // use the CPU's statically allocated write request and packet objects
335 Request *req = data_write_req;
336 Packet *pkt = data_write_pkt;
337
338 req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
339
340 if (traceData) {
341 traceData->setAddr(addr);
342 }
343
344 // translate to physical address
345 Fault fault = thread->translateDataWriteReq(req);
346
347 // Now do the access.
348 if (fault == NoFault) {
349 data = htog(data);
350 pkt->reinitFromRequest();
351 pkt->dataStatic(&data);
352
353 dcache_latency = dcachePort.sendAtomic(pkt);
354 dcache_access = true;
355
356 assert(pkt->result == Packet::Success);
357
358 if (res && req->getFlags() & LOCKED) {
359 *res = req->getScResult();
360 }
361 }
362
363 // This will need a new way to tell if it's hooked up to a cache or not.
364 if (req->getFlags() & UNCACHEABLE)
365 recordEvent("Uncached Write");
366
367 // If the write needs to have a fault on the access, consider calling
368 // changeStatus() and changing it to "bad addr write" or something.
369 return fault;
370}
371
372
373#ifndef DOXYGEN_SHOULD_SKIP_THIS
374template
375Fault
376AtomicSimpleCPU::write(uint64_t data, Addr addr,
377 unsigned flags, uint64_t *res);
378
379template
380Fault
381AtomicSimpleCPU::write(uint32_t data, Addr addr,
382 unsigned flags, uint64_t *res);
383
384template
385Fault
386AtomicSimpleCPU::write(uint16_t data, Addr addr,
387 unsigned flags, uint64_t *res);
388
389template
390Fault
391AtomicSimpleCPU::write(uint8_t data, Addr addr,
392 unsigned flags, uint64_t *res);
393
394#endif //DOXYGEN_SHOULD_SKIP_THIS
395
396template<>
397Fault
398AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
399{
400 return write(*(uint64_t*)&data, addr, flags, res);
401}
402
403template<>
404Fault
405AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
406{
407 return write(*(uint32_t*)&data, addr, flags, res);
408}
409
410
411template<>
412Fault
413AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
414{
415 return write((uint32_t)data, addr, flags, res);
416}
417
418
419void
420AtomicSimpleCPU::tick()
421{
422 Tick latency = cycles(1); // instruction takes one cycle by default
423
424 for (int i = 0; i < width; ++i) {
425 numCycles++;
426
427 checkForInterrupts();
428
429 Fault fault = setupFetchRequest(ifetch_req);
430
431 if (fault == NoFault) {
432 ifetch_pkt->reinitFromRequest();
433
434 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
435 // ifetch_req is initialized to read the instruction directly
436 // into the CPU object's inst field.
437
438 dcache_access = false; // assume no dcache access
439 preExecute();
440 fault = curStaticInst->execute(this, traceData);
441 postExecute();
442
443 if (simulate_stalls) {
444 Tick icache_stall = icache_latency - cycles(1);
445 Tick dcache_stall =
446 dcache_access ? dcache_latency - cycles(1) : 0;
447 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
448 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
449 latency += cycles(stall_cycles+1);
450 else
451 latency += cycles(stall_cycles);
452 }
453
454 }
455
456 advancePC(fault);
457 }
458
459 if (_status != Idle)
460 tickEvent.schedule(curTick + latency);
461}
462
463
464////////////////////////////////////////////////////////////////////////
465//
466// AtomicSimpleCPU Simulation Object
467//
468BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
469
470 Param<Counter> max_insts_any_thread;
471 Param<Counter> max_insts_all_threads;
472 Param<Counter> max_loads_any_thread;
473 Param<Counter> max_loads_all_threads;
474 Param<Tick> progress_interval;
475 SimObjectParam<MemObject *> mem;
476 SimObjectParam<System *> system;
477
478#if FULL_SYSTEM
479 SimObjectParam<AlphaITB *> itb;
480 SimObjectParam<AlphaDTB *> dtb;
481 Param<int> cpu_id;
482 Param<Tick> profile;
483#else
484 SimObjectParam<Process *> workload;
485#endif // FULL_SYSTEM
486
487 Param<int> clock;
488
489 Param<bool> defer_registration;
490 Param<int> width;
491 Param<bool> function_trace;
492 Param<Tick> function_trace_start;
493 Param<bool> simulate_stalls;
494
495END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
496
497BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
498
499 INIT_PARAM(max_insts_any_thread,
500 "terminate when any thread reaches this inst count"),
501 INIT_PARAM(max_insts_all_threads,
502 "terminate when all threads have reached this inst count"),
503 INIT_PARAM(max_loads_any_thread,
504 "terminate when any thread reaches this load count"),
505 INIT_PARAM(max_loads_all_threads,
506 "terminate when all threads have reached this load count"),
507 INIT_PARAM(progress_interval, "Progress interval"),
508 INIT_PARAM(mem, "memory"),
509 INIT_PARAM(system, "system object"),
510
511#if FULL_SYSTEM
512 INIT_PARAM(itb, "Instruction TLB"),
513 INIT_PARAM(dtb, "Data TLB"),
514 INIT_PARAM(cpu_id, "processor ID"),
515 INIT_PARAM(profile, ""),
516#else
517 INIT_PARAM(workload, "processes to run"),
518#endif // FULL_SYSTEM
519
520 INIT_PARAM(clock, "clock speed"),
521 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
522 INIT_PARAM(width, "cpu width"),
523 INIT_PARAM(function_trace, "Enable function trace"),
524 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
525 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
526
527END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
528
529
530CREATE_SIM_OBJECT(AtomicSimpleCPU)
531{
532 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
533 params->name = getInstanceName();
534 params->numberOfThreads = 1;
535 params->max_insts_any_thread = max_insts_any_thread;
536 params->max_insts_all_threads = max_insts_all_threads;
537 params->max_loads_any_thread = max_loads_any_thread;
538 params->max_loads_all_threads = max_loads_all_threads;
539 params->progress_interval = progress_interval;
540 params->deferRegistration = defer_registration;
541 params->clock = clock;
542 params->functionTrace = function_trace;
543 params->functionTraceStart = function_trace_start;
544 params->width = width;
545 params->simulate_stalls = simulate_stalls;
546 params->mem = mem;
547 params->system = system;
548
549#if FULL_SYSTEM
550 params->itb = itb;
551 params->dtb = dtb;
552 params->cpu_id = cpu_id;
553 params->profile = profile;
554#else
555 params->process = workload;
556#endif
557
558 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
559 return cpu;
560}
561
562REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
563