1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/atomic.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36
37using namespace std;
38using namespace TheISA;
39
40AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
41 : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
42{
43}
44
45
46void
47AtomicSimpleCPU::TickEvent::process()
48{
49 cpu->tick();
50}
51
52const char *
53AtomicSimpleCPU::TickEvent::description()
54{
55 return "AtomicSimpleCPU tick event";
56}
57
58Port *
59AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
60{
61 if (if_name == "dcache_port")
62 return &dcachePort;
63 else if (if_name == "icache_port")
64 return &icachePort;
65 else
66 panic("No Such Port\n");
67}
68
69void
70AtomicSimpleCPU::init()
71{
72 //Create Memory Ports (conect them up)
73// Port *mem_dport = mem->getPort("");
74// dcachePort.setPeer(mem_dport);
75// mem_dport->setPeer(&dcachePort);
76
77// Port *mem_iport = mem->getPort("");
78// icachePort.setPeer(mem_iport);
79// mem_iport->setPeer(&icachePort);
80
81 BaseCPU::init();
82#if FULL_SYSTEM
83 for (int i = 0; i < threadContexts.size(); ++i) {
84 ThreadContext *tc = threadContexts[i];
85
86 // initialize CPU, including PC
87 TheISA::initCPU(tc, tc->readCpuId());
88 }
89#endif
90}
91
92bool
93AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
94{
95 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
96 return true;
97}
98
99Tick
100AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
101{
102 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
103 return curTick;
104}
105
106void
107AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
108{
109 panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
110}
111
112void
113AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
114{
115 if (status == RangeChange)
116 return;
117
118 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
119}
120
121void
122AtomicSimpleCPU::CpuPort::recvRetry()
123{
124 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
125}
126
127
128AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
129 : BaseSimpleCPU(p), tickEvent(this),
130 width(p->width), simulate_stalls(p->simulate_stalls),
131 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
132{
133 _status = Idle;
134
135 // @todo fix me and get the real cpu id & thread number!!!
136 ifetch_req = new Request();
137 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
138 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
139 ifetch_pkt->dataStatic(&inst);
140
141 data_read_req = new Request();
142 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
143 data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
144 Packet::Broadcast);
145 data_read_pkt->dataStatic(&dataReg);
146
147 data_write_req = new Request();
148 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
149 data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
150 Packet::Broadcast);
151}
152
153
154AtomicSimpleCPU::~AtomicSimpleCPU()
155{
156}
157
158void
159AtomicSimpleCPU::serialize(ostream &os)
160{
161 SERIALIZE_ENUM(_status);
162 BaseSimpleCPU::serialize(os);
163 nameOut(os, csprintf("%s.tickEvent", name()));
164 tickEvent.serialize(os);
165}
166
167void
168AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
169{
170 UNSERIALIZE_ENUM(_status);
171 BaseSimpleCPU::unserialize(cp, section);
172 tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
173}
174
175void
176AtomicSimpleCPU::switchOut()
177{
178 assert(status() == Running || status() == Idle);
179 _status = SwitchedOut;
180
181 tickEvent.squash();
182}
183
184
185void
186AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
187{
188 BaseCPU::takeOverFrom(oldCPU);
189
190 assert(!tickEvent.scheduled());
191
192 // if any of this CPU's ThreadContexts are active, mark the CPU as
193 // running and schedule its tick event.
194 for (int i = 0; i < threadContexts.size(); ++i) {
195 ThreadContext *tc = threadContexts[i];
196 if (tc->status() == ThreadContext::Active && _status != Running) {
197 _status = Running;
198 tickEvent.schedule(curTick);
199 break;
200 }
201 }
202}
203
204
205void
206AtomicSimpleCPU::activateContext(int thread_num, int delay)
207{
208 assert(thread_num == 0);
209 assert(thread);
210
211 assert(_status == Idle);
212 assert(!tickEvent.scheduled());
213
214 notIdleFraction++;
215 tickEvent.schedule(curTick + cycles(delay));
216 _status = Running;
217}
218
219
220void
221AtomicSimpleCPU::suspendContext(int thread_num)
222{
223 assert(thread_num == 0);
224 assert(thread);
225
226 assert(_status == Running);
227
228 // tick event may not be scheduled if this gets called from inside
229 // an instruction's execution, e.g. "quiesce"
230 if (tickEvent.scheduled())
231 tickEvent.deschedule();
232
233 notIdleFraction--;
234 _status = Idle;
235}
236
237
238template <class T>
239Fault
240AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
241{
242 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
243
244 if (traceData) {
245 traceData->setAddr(addr);
246 }
247
248 // translate to physical address
249 Fault fault = thread->translateDataReadReq(data_read_req);
250
251 // Now do the access.
252 if (fault == NoFault) {
253 data_read_pkt->reinitFromRequest();
254
255 dcache_latency = dcachePort.sendAtomic(data_read_pkt);
256 dcache_access = true;
257
258 assert(data_read_pkt->result == Packet::Success);
259 data = data_read_pkt->get<T>();
260
261 }
262
263 // This will need a new way to tell if it has a dcache attached.
264 if (data_read_req->getFlags() & UNCACHEABLE)
265 recordEvent("Uncached Read");
266
267 return fault;
268}
269
270#ifndef DOXYGEN_SHOULD_SKIP_THIS
271
272template
273Fault
274AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
275
276template
277Fault
278AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
279
280template
281Fault
282AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
283
284template
285Fault
286AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
287
288#endif //DOXYGEN_SHOULD_SKIP_THIS
289
290template<>
291Fault
292AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
293{
294 return read(addr, *(uint64_t*)&data, flags);
295}
296
297template<>
298Fault
299AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
300{
301 return read(addr, *(uint32_t*)&data, flags);
302}
303
304
305template<>
306Fault
307AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
308{
309 return read(addr, (uint32_t&)data, flags);
310}
311
312
313template <class T>
314Fault
315AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
316{
317 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
318
319 if (traceData) {
320 traceData->setAddr(addr);
321 }
322
323 // translate to physical address
324 Fault fault = thread->translateDataWriteReq(data_write_req);
325
326 // Now do the access.
327 if (fault == NoFault) {
328 data = htog(data);
329 data_write_pkt->reinitFromRequest();
330 data_write_pkt->dataStatic(&data);
331
332 dcache_latency = dcachePort.sendAtomic(data_write_pkt);
333 dcache_access = true;
334
335 assert(data_write_pkt->result == Packet::Success);
336
337 if (res && data_write_req->getFlags() & LOCKED) {
338 *res = data_write_req->getScResult();
339 }
340 }
341
342 // This will need a new way to tell if it's hooked up to a cache or not.
343 if (data_write_req->getFlags() & UNCACHEABLE)
344 recordEvent("Uncached Write");
345
346 // If the write needs to have a fault on the access, consider calling
347 // changeStatus() and changing it to "bad addr write" or something.
348 return fault;
349}
350
351
352#ifndef DOXYGEN_SHOULD_SKIP_THIS
353template
354Fault
355AtomicSimpleCPU::write(uint64_t data, Addr addr,
356 unsigned flags, uint64_t *res);
357
358template
359Fault
360AtomicSimpleCPU::write(uint32_t data, Addr addr,
361 unsigned flags, uint64_t *res);
362
363template
364Fault
365AtomicSimpleCPU::write(uint16_t data, Addr addr,
366 unsigned flags, uint64_t *res);
367
368template
369Fault
370AtomicSimpleCPU::write(uint8_t data, Addr addr,
371 unsigned flags, uint64_t *res);
372
373#endif //DOXYGEN_SHOULD_SKIP_THIS
374
375template<>
376Fault
377AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
378{
379 return write(*(uint64_t*)&data, addr, flags, res);
380}
381
382template<>
383Fault
384AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
385{
386 return write(*(uint32_t*)&data, addr, flags, res);
387}
388
389
390template<>
391Fault
392AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
393{
394 return write((uint32_t)data, addr, flags, res);
395}
396
397
398void
399AtomicSimpleCPU::tick()
400{
401 Tick latency = cycles(1); // instruction takes one cycle by default
402
403 for (int i = 0; i < width; ++i) {
404 numCycles++;
405
406 checkForInterrupts();
407
408 Fault fault = setupFetchRequest(ifetch_req);
409
410 if (fault == NoFault) {
411 ifetch_pkt->reinitFromRequest();
412
413 Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
414 // ifetch_req is initialized to read the instruction directly
415 // into the CPU object's inst field.
416
417 dcache_access = false; // assume no dcache access
418 preExecute();
419 fault = curStaticInst->execute(this, traceData);
420 postExecute();
421
422 if (simulate_stalls) {
423 Tick icache_stall = icache_latency - cycles(1);
424 Tick dcache_stall =
425 dcache_access ? dcache_latency - cycles(1) : 0;
426 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
427 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
428 latency += cycles(stall_cycles+1);
429 else
430 latency += cycles(stall_cycles);
431 }
432
433 }
434
435 advancePC(fault);
436 }
437
438 if (_status != Idle)
439 tickEvent.schedule(curTick + latency);
440}
441
442
443////////////////////////////////////////////////////////////////////////
444//
445// AtomicSimpleCPU Simulation Object
446//
447BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
448
449 Param<Counter> max_insts_any_thread;
450 Param<Counter> max_insts_all_threads;
451 Param<Counter> max_loads_any_thread;
452 Param<Counter> max_loads_all_threads;
453 SimObjectParam<MemObject *> mem;
454
455#if FULL_SYSTEM
456 SimObjectParam<AlphaITB *> itb;
457 SimObjectParam<AlphaDTB *> dtb;
458 SimObjectParam<System *> system;
459 Param<int> cpu_id;
460 Param<Tick> profile;
461#else
462 SimObjectParam<Process *> workload;
463#endif // FULL_SYSTEM
464
465 Param<int> clock;
466
467 Param<bool> defer_registration;
468 Param<int> width;
469 Param<bool> function_trace;
470 Param<Tick> function_trace_start;
471 Param<bool> simulate_stalls;
472
473END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
474
475BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
476
477 INIT_PARAM(max_insts_any_thread,
478 "terminate when any thread reaches this inst count"),
479 INIT_PARAM(max_insts_all_threads,
480 "terminate when all threads have reached this inst count"),
481 INIT_PARAM(max_loads_any_thread,
482 "terminate when any thread reaches this load count"),
483 INIT_PARAM(max_loads_all_threads,
484 "terminate when all threads have reached this load count"),
485 INIT_PARAM(mem, "memory"),
486
487#if FULL_SYSTEM
488 INIT_PARAM(itb, "Instruction TLB"),
489 INIT_PARAM(dtb, "Data TLB"),
490 INIT_PARAM(system, "system object"),
491 INIT_PARAM(cpu_id, "processor ID"),
492 INIT_PARAM(profile, ""),
493#else
494 INIT_PARAM(workload, "processes to run"),
495#endif // FULL_SYSTEM
496
497 INIT_PARAM(clock, "clock speed"),
498 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
499 INIT_PARAM(width, "cpu width"),
500 INIT_PARAM(function_trace, "Enable function trace"),
501 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
502 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
503
504END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
505
506
507CREATE_SIM_OBJECT(AtomicSimpleCPU)
508{
509 AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
510 params->name = getInstanceName();
511 params->numberOfThreads = 1;
512 params->max_insts_any_thread = max_insts_any_thread;
513 params->max_insts_all_threads = max_insts_all_threads;
514 params->max_loads_any_thread = max_loads_any_thread;
515 params->max_loads_all_threads = max_loads_all_threads;
516 params->deferRegistration = defer_registration;
517 params->clock = clock;
518 params->functionTrace = function_trace;
519 params->functionTraceStart = function_trace_start;
520 params->width = width;
521 params->simulate_stalls = simulate_stalls;
522 params->mem = mem;
523
524#if FULL_SYSTEM
525 params->itb = itb;
526 params->dtb = dtb;
527 params->system = system;
528 params->cpu_id = cpu_id;
529 params->profile = profile;
530#else
531 params->process = workload;
532#endif
533
534 AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
535 return cpu;
536}
537
538REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
539