1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/simple/atomic.hh"
49#include "cpu/exetrace.hh"
50#include "debug/Drain.hh"
51#include "debug/ExecFaulting.hh"
52#include "debug/SimpleCPU.hh"
53#include "mem/packet.hh"
54#include "mem/packet_access.hh"

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104
105AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
106 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
107 simulate_data_stalls(p->simulate_data_stalls),
108 simulate_inst_stalls(p->simulate_inst_stalls),
109 drain_manager(NULL),
110 icachePort(name() + ".icache_port", this),
111 dcachePort(name() + ".dcache_port", this),
112 fastmem(p->fastmem)
113{
114 _status = Idle;
115}
116
117
118AtomicSimpleCPU::~AtomicSimpleCPU()
119{
120 if (tickEvent.scheduled()) {
121 deschedule(tickEvent);
122 }
123}
124
125unsigned int
126AtomicSimpleCPU::drain(DrainManager *dm)
127{
128 assert(!drain_manager);
129 if (switchedOut())
130 return 0;

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529 postExecute();
530 }
531
532 // @todo remove me after debugging with legion done
533 if (curStaticInst && (!curStaticInst->isMicroop() ||
534 curStaticInst->isFirstMicroop()))
535 instCnt++;
536
537 Tick stall_ticks = 0;
538 if (simulate_inst_stalls && icache_access)
539 stall_ticks += icache_latency;
540
541 if (simulate_data_stalls && dcache_access)
542 stall_ticks += dcache_latency;
543
544 if (stall_ticks) {

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567
568
569void
570AtomicSimpleCPU::printAddr(Addr a)
571{
572 dcachePort.printAddr(a);
573}
574
575
576////////////////////////////////////////////////////////////////////////
577//
578// AtomicSimpleCPU Simulation Object
579//
580AtomicSimpleCPU *
581AtomicSimpleCPUParams::create()
582{
583 numThreads = 1;
584 if (!FullSystem && workload.size() != 1)
585 panic("only one workload allowed");
586 return new AtomicSimpleCPU(this);
587}