1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright

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34#include "base/bigint.hh"
35#include "config/the_isa.hh"
36#include "cpu/simple/atomic.hh"
37#include "cpu/exetrace.hh"
38#include "debug/ExecFaulting.hh"
39#include "debug/SimpleCPU.hh"
40#include "mem/packet.hh"
41#include "mem/packet_access.hh"
42#include "params/AtomicSimpleCPU.hh"
43#include "sim/faults.hh"
44#include "sim/system.hh"
45#include "sim/full_system.hh"
46
47using namespace std;
48using namespace TheISA;
49

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60}
61
62const char *
63AtomicSimpleCPU::TickEvent::description() const
64{
65 return "AtomicSimpleCPU tick";
66}
67
68MasterPort &
69AtomicSimpleCPU::getMasterPort(const string &if_name, int idx)
70{
71 if (if_name == "physmem_port") {
72 hasPhysMemPort = true;
73 return physmemPort;
74 } else {
75 return BaseCPU::getMasterPort(if_name, idx);
76 }
77}
78
79void
80AtomicSimpleCPU::init()
81{
82 BaseCPU::init();
83
84 // Initialise the ThreadContext's memory proxies
85 tcBase()->initMemProxies(tcBase());
86
87 if (FullSystem) {
88 ThreadID size = threadContexts.size();
89 for (ThreadID i = 0; i < size; ++i) {
90 ThreadContext *tc = threadContexts[i];
91 // initialize CPU, including PC
92 TheISA::initCPU(tc, tc->contextId());
93 }
94 }
95
96 if (hasPhysMemPort) {
97 AddrRangeList pmAddrList = physmemPort.getSlavePort().getAddrRanges();
98 physMemAddr = *pmAddrList.begin();
99 }
100 // Atomic doesn't do MT right now, so contextId == threadId
101 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
102 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
103 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
104}
105
106AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
107 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
108 simulate_data_stalls(p->simulate_data_stalls),
109 simulate_inst_stalls(p->simulate_inst_stalls),
110 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
111 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
112{
113 _status = Idle;
114}
115
116
117AtomicSimpleCPU::~AtomicSimpleCPU()
118{
119 if (tickEvent.scheduled()) {

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276 Packet pkt = Packet(req,
277 req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
278 Packet::Broadcast);
279 pkt.dataStatic(data);
280
281 if (req->isMmappedIpr())
282 dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
283 else {
284 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
285 dcache_latency += physmemPort.sendAtomic(&pkt);
286 else
287 dcache_latency += dcachePort.sendAtomic(&pkt);
288 }
289 dcache_access = true;
290
291 assert(!pkt.isError());
292
293 if (req->isLLSC()) {

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378 if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) {
379 Packet pkt = Packet(req, cmd, Packet::Broadcast);
380 pkt.dataStatic(data);
381
382 if (req->isMmappedIpr()) {
383 dcache_latency +=
384 TheISA::handleIprWrite(thread->getTC(), &pkt);
385 } else {
386 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
387 dcache_latency += physmemPort.sendAtomic(&pkt);
388 else
389 dcache_latency += dcachePort.sendAtomic(&pkt);
390 }
391 dcache_access = true;
392 assert(!pkt.isError());
393
394 if (req->isSwap()) {
395 assert(res);

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474 //Fetch more instruction memory if necessary
475 //if(predecoder.needMoreBytes())
476 //{
477 icache_access = true;
478 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
479 Packet::Broadcast);
480 ifetch_pkt.dataStatic(&inst);
481
482 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
483 icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
484 else
485 icache_latency = icachePort.sendAtomic(&ifetch_pkt);
486
487 assert(!ifetch_pkt.isError());
488
489 // ifetch_req is initialized to read the instruction directly
490 // into the CPU object's inst field.
491 //}

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