1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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37#include "cpu/exetrace.hh"
38#include "debug/ExecFaulting.hh"
39#include "debug/SimpleCPU.hh"
40#include "mem/packet.hh"
41#include "mem/packet_access.hh"
42#include "params/AtomicSimpleCPU.hh"
43#include "sim/faults.hh"
44#include "sim/system.hh"
45
46using namespace std;
47using namespace TheISA;
48
49AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
50 : Event(CPU_Tick_Pri), cpu(c)
51{
52}

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78 else
79 panic("No Such Port\n");
80}
81
82void
83AtomicSimpleCPU::init()
84{
85 BaseCPU::init();
86#if FULL_SYSTEM
87 ThreadID size = threadContexts.size();
88 for (ThreadID i = 0; i < size; ++i) {
89 ThreadContext *tc = threadContexts[i];
90
91 // initialize CPU, including PC
92 TheISA::initCPU(tc, tc->contextId());
93 }
94
95 // Initialise the ThreadContext's memory proxies
96 tcBase()->initMemProxies(tcBase());
97#endif
98 if (hasPhysMemPort) {
99 AddrRangeList pmAddrList = physmemPort.getPeer()->getAddrRanges();
100 physMemAddr = *pmAddrList.begin();
101 }
102 // Atomic doesn't do MT right now, so contextId == threadId
103 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
104 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
105 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
106}
107
108AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
109 : BaseSimpleCPU(p), tickEvent(this), width(p->width), locked(false),
110 simulate_data_stalls(p->simulate_data_stalls),
111 simulate_inst_stalls(p->simulate_inst_stalls),
112 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
113 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
114{
115 _status = Idle;
116}
117
118
119AtomicSimpleCPU::~AtomicSimpleCPU()
120{
121 if (tickEvent.scheduled()) {
122 deschedule(tickEvent);
123 }

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169
170 tickEvent.squash();
171}
172
173
174void
175AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
176{
177 BaseCPU::takeOverFrom(oldCPU);
178
179 assert(!tickEvent.scheduled());
180
181 // if any of this CPU's ThreadContexts are active, mark the CPU as
182 // running and schedule its tick event.
183 ThreadID size = threadContexts.size();
184 for (ThreadID i = 0; i < size; ++i) {
185 ThreadContext *tc = threadContexts[i];

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195 assert(threadContexts.size() == 1);
196 ifetch_req.setThreadContext(_cpuId, 0); // Add thread ID if we add MT
197 data_read_req.setThreadContext(_cpuId, 0); // Add thread ID here too
198 data_write_req.setThreadContext(_cpuId, 0); // Add thread ID here too
199}
200
201
202void
203AtomicSimpleCPU::activateContext(ThreadID thread_num, int delay)
204{
205 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
206
207 assert(thread_num == 0);
208 assert(thread);
209
210 assert(_status == Idle);
211 assert(!tickEvent.scheduled());
212
213 notIdleFraction++;
214 numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
215
216 //Make sure ticks are still on multiples of cycles
217 schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
218 _status = Running;
219}
220
221
222void
223AtomicSimpleCPU::suspendContext(ThreadID thread_num)
224{
225 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
226
227 assert(thread_num == 0);
228 assert(thread);
229
230 if (_status == Idle)
231 return;

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556//
557// AtomicSimpleCPU Simulation Object
558//
559AtomicSimpleCPU *
560AtomicSimpleCPUParams::create()
561{
562 numThreads = 1;
563#if !FULL_SYSTEM
564 if (workload.size() != 1)
565 panic("only one workload allowed");
566#endif
567 return new AtomicSimpleCPU(this);
568}