1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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446Fault
447AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
448{
449 // use the CPU's statically allocated write request and packet objects
450 Request *req = &data_write_req;
451
452 if (traceData) {
453 traceData->setAddr(addr);
454 }
455
456 //The block size of our peer.
457 unsigned blockSize = dcachePort.peerBlockSize();
458 //The size of the data we're trying to read.
459 int dataSize = sizeof(T);
460
461 uint8_t * dataPtr = (uint8_t *)&data;

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525 // This will need a new way to tell if it's hooked up to a cache or not.
526 if (req->isUncacheable())
527 recordEvent("Uncached Write");
528
529 //If there's a fault or we don't need to access a second cache line,
530 //stop now.
531 if (fault != NoFault || secondAddr <= addr)
532 {
533 // If the write needs to have a fault on the access, consider
534 // calling changeStatus() and changing it to "bad addr write"
535 // or something.
536 if (traceData) {
537 traceData->setData(gtoh(data));
538 }
539 if (req->isLocked() && fault == NoFault) {
540 assert(locked);
541 locked = false;
542 }
543 if (fault != NoFault && req->isPrefetch()) {
544 return NoFault;
545 } else {
546 return fault;

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